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2018-01-09target/xtensa: add internal/noop SRs and opcodesMax Filippov
Add two special registers: MMID and DDR: - MMID is write-only and the only side effect of writing to it is output to the trace port, which is not emulated; - DDR is only accessible in debug mode, which is not emulated. Add two debug-mode-only opcodes: - rfdd and rfdo do return from the debug mode, which is not emulated. Add three internal opcodes for full MMU: - hwwdtlba and hwwitlba are the internal opcodes that write a value into autoupdate DTLB or ITLB entry. - ldpte is internal opcode that loads PTE entry that covers the most recent page fault address. None of these three opcodes may appear in a valid instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: drop DisasContext::litbaseMax Filippov
It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09target/xtensa: use libisa for instruction decodingMax Filippov
Replace manual opcode analysis with libisa-based code. This makes it possible to support variable-encoding instructions of the core ISA, like const16, and will allow to support advanced Xtensa features, like FLIX and TIE. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: switch fsf to libisaMax Filippov
Autogenerated xtensa-modules.c is added by the import_core.sh script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: switch dc233c to libisaMax Filippov
Autogenerated xtensa-modules.c is added by the import_core.sh script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: switch dc232b to libisaMax Filippov
Autogenerated xtensa-modules.c is added by the import_core.sh script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: update import_core.sh script for libisaMax Filippov
Extract xtensa-modules.c from the overlay, fix up known issues, include it into the core-$NAME.c. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: extract FPU2000 opcode translatorsMax Filippov
FPU2000 implements basic single-precision floating point operations and can be replaced with a different implementation, like DFPU or HiFi. Move FPU2000 opcode translators into separate functions and list them in a separate array. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: extract core opcode translatorsMax Filippov
Move implementations of core opcodes into separate translation functions. Introduce data structures for mapping opcode name to translator function. Make an array of core opcode/translator structures. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: import libisa sourceMax Filippov
The canonical way of dealing with Xtensa instructions decoding and encoding is through the libisa. Libisa is a configuration-independent library with a stable interface plus generated configuration-specific xtensa-modules.c file with implementations of decoding and encoding functions. Libisa is MIT-licensed and originally disributed xtensa-modules.c files are also MIT-licensed and are available as a part of xtensa configuration overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-18target/xtensa: pass actual frame size to the entry helperMax Filippov
Currently 'entry' opcode helper accepts frame size divided by 8, as it is encoded in the opcode. Make it more natural and accept actual frame size instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-10-30Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86/cpu/numa queue, 2017-10-27 # gpg: Signature made Fri 27 Oct 2017 15:17:12 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: (39 commits) x86: Skip check apic_id_limit for Xen numa: fixup parsed NumaNodeOptions earlier mips: r4k: replace cpu_model with cpu_type mips: mipssim: replace cpu_model with cpu_type mips: Magnum/Acer Pica 61: replace cpu_model with cpu_type mips: fulong2e: replace cpu_model with cpu_type mips: malta/boston: replace cpu_model with cpu_type mips: use object_new() instead of gnew()+object_initialize() sparc: leon3: use generic cpu_model parsing sparc: sparc: use generic cpu_model parsing sparc: sun4u/sun4v/niagara: use generic cpu_model parsing sparc: cleanup cpu type name composition tricore: use generic cpu_model parsing tricore: cleanup cpu type name composition unicore32: use generic cpu_model parsing unicore32: cleanup cpu type name composition xtensa: lx60/lx200/ml605/kc705: use generic cpu_model parsing xtensa: sim: use generic cpu_model parsing xtensa: cleanup cpu type name composition sh4: remove SuperHCPUClass::name field ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-27xtensa: cleanup cpu type name compositionIgor Mammedov
use new XTENSA_CPU_TYPE_NAME to compose CPU type name to bring xtensa in line with all other targets that will similar macro. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-25-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
2017-10-25disas: Remove unused flags argumentsRichard Henderson
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Acked-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
and clean every implementation. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170917232842.14544-1-f4bug@amsat.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-26target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macroAlistair Francis
Instead of using the hardcoded (MemTxAttrs){0} for no memory attributes let's use the already defined MEMTXATTRS_UNSPECIFIED macro instead. This is technically a change of behaviour as MEMTXATTRS_UNSPECIFIED sets the unspecified field to 1, but it doesn't look like anything is checking this field. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-01xtensa: replace cpu_xtensa_init() with cpu_generic_init()Igor Mammedov
call xtensa_irq_init() at realize time which makes cpu_xtensa_init() like generic cpu creation function. As result we can replace it with cpu_generic_init() which does the same job, reducing code duplication a bit. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1503592308-93913-16-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-14char: add backend hotswap handlerAnton Nefedov
Frontends should have an interface to setup the handler of a backend change. The interface will be used in the next commits Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <1499342940-56739-3-git-send-email-anton.nefedov@virtuozzo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-07-11target/xtensa: gdbstub: drop dead return statementMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-06-06target/xtensa: handle unknown registers in gdbstubMax Filippov
Xtensa cores may have registers of types/sizes not supported by the gdbstub accessors. Ignore writes to such registers and return zero on read, but always return correct register size, so that gdb on the other side is able to access all registers in the packet holding unsupported registers in the middle. This fixes gdb interaction with cores that have vector/custom TIE registers. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: support output to chardev consoleMax Filippov
In semihosting mode QEMU allows guest to read and write host file descriptors directly, including descriptors 0..2, a.k.a. stdin, stdout and stderr. Sometimes it's desirable to have semihosting console controlled by -serial option, e.g. to connect it to network. Add semihosting console to xtensa-semi.c, open it in the 'sim' machine in the presence of -serial option and direct stdout and stderr to it when it's present. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: fix return value of read/write simcallsMax Filippov
Return value of read/write simcalls is not calculated correctly in case of operations crossing page boundary and in case of short reads/writes. Read and write simcalls should return the size of data actually read/written or -1 in case of error. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-06-06target/xtensa: fix mapping direction in read/write simcallsMax Filippov
Read and write simcalls map physical memory to access I/O buffers, but 'read' simcall need to map it for writing and 'write' simcall need to map it for reading, i.e. the opposite of what they do now. Fix that. Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-03-18Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into stagingPeter Maydell
target/xtensa fixes for 2.9: - fix build failure when FDT support is not enabled; - correctly pass command line arguments to semihosting guests. # gpg: Signature made Fri 17 Mar 2017 18:14:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170317-xtensa: target/xtensa: fix semihosting argc/argv implementation target/xtensa: xtfpga: load DTB only when FDT support is enabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-03-11target/xtensa: fix semihosting argc/argv implementationMax Filippov
So far xtensa provides fixed dummy argc/argv for the corresponding semihosting calls. Now that there are semihosting_get_argc and semihosting_get_arg, use them to pass actual command line arguments to guest. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-03-09target/xtensa: hold BQL for interrupt processingAlex Bennée
Make sure we have the BQL held when processing interrupts. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-23target/xtensa: add two missing headers to core import scriptMax Filippov
Include qemu/osdep.h and qemu-common.h at the beginning of imported xtensa core source file. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-23target/xtensa: sim: instantiate local memoriesMax Filippov
Xtensa core may have a number of RAM and ROM areas configured. Record their size and location from the core configuration overlay and instantiate them as RAM regions in the SIM machine. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth
When running certain HMP commands ("info registers", "info cpustats", "info tlb", "nmi", "memsave" or dumping virtual memory) with the "none" machine, QEMU crashes with a segmentation fault. This happens because the "none" machine does not have any CPUs by default, but these HMP commands did not check for a valid CPU pointer yet. Add such checks now, so we get an error message about the missing CPU instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1484309555-1935-1-git-send-email-thuth@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-01-25Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell
target/xtensa updates: - refactor CCOUNT/CCOMPARE (use QEMU timers instead of instruction counting); - support icount; run target/xtensa TCG tests with icount; - implement SMP prerequisites: static vector selection, RUNSTALL and RER/WER. # gpg: Signature made Wed 25 Jan 2017 00:27:51 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170124-xtensa: target-xtensa: implement RER/WER instructions target/xtensa: tests: clean up interrupt tests target/xtensa: tests: add memctl test target/xtensa: implement MEMCTL SR target/xtensa: fix ICACHE/DCACHE options detection target/xtensa: tests: add ccount write tests target/xtensa: tests: replace hardcoded interrupt masks target/xtensa: tests: fix timer tests target/xtensa: tests: run tests with icount target/xtensa: don't continue translation after exception target/xtensa: support icount target/xtensa: refactor CCOUNT/CCOMPARE target/xtensa: implement RUNSTALL target/xtensa: add static vectors selection Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov
RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov
MEMCTL SR controls zero overhead loop buffer and number of ways enabled in L1 caches. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov
Configuration overlay does not explicitly say whether there are ICACHE and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect if corresponding cache option is enabled, but that's not correct: on cores without cache these macros are defined as 1, not as 0. Check XCHAL_[ID]CACHE_SIZE instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: don't continue translation after exceptionMax Filippov
There's no point in continuing translating guest instructions once an unconditional exception is thrown. There's also no point in updating pc before any instruction is translated, don't do it. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: support icountMax Filippov
Delimit each instruction that may access timers or IRQ state with qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with -icount option. Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec recalculate how long this CPU is allowed to run. RSR now may need to terminate TB, but it can't be done in RSR handler because the same handler is used for XSR together with WSR handler, which may also need to terminate TB. Change RSR and WSR handlers return type to bool indicating whether TB termination is needed (RSR) or has been done (WSR), and add TB termination after RSR/WSR dispatcher call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov
Xtensa cores may have a register (CCOUNT) that counts core clock cycles. It may also have a number of registers (CCOMPAREx); when CCOUNT value passes the value of CCOMPAREx, timer interrupt x is raised. Currently xtensa target counts a number of completed instructions and assumes that for CCOUNT one instruction takes one cycle to complete. It calls helper function to update CCOUNT register at every TB end and raise timer interrupts. This scheme works very predictably and doesn't have noticeable performance impact, but it is hard to use with multiple synchronized processors, especially with coming MTTCG. Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL. Use native QEMU timers for CCOMPARE timers, one timer for each register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: implement RUNSTALLMax Filippov
RUNSTALL signal stalls core execution while it's applied. It is widely used in multicore configurations to control activity of additional cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15target/xtensa: add static vectors selectionMax Filippov
Xtensa cores may have two distinct addresses for the static vectors group. Provide a function to select one of them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-10target-xtensa: Use clrsb helperRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-xtensa: Use clz opcodeRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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