Age | Commit message (Expand) | Author |
2018-02-05 | qdev: use device_class_set_parent_realize/unrealize/reset() | Philippe Mathieu-Daudé |
2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier |
2018-01-24 | Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging | Peter Maydell |
2018-01-22 | target/xtensa: disas/xtensa: fix coverity warnings | Max Filippov |
2018-01-22 | target/xtensa: add sample_controller core | Max Filippov |
2018-01-22 | target/xtensa: allow different default CPU for MMU/noMMU | Max Filippov |
2018-01-12 | target/xtensa: Remove duplicate typedef of DisasContext | Peter Maydell |
2018-01-11 | target/xtensa: add de212 core | Max Filippov |
2018-01-11 | target/xtensa: fix default sysrom/sysram addresses | Max Filippov |
2018-01-09 | target/xtensa: implement disassembler | Max Filippov |
2018-01-09 | target/xtensa: implement const16 | Max Filippov |
2018-01-09 | target/xtensa: implement GPIO32 | Max Filippov |
2018-01-09 | target/xtensa: implement salt/saltu | Max Filippov |
2018-01-09 | target/xtensa: add internal/noop SRs and opcodes | Max Filippov |
2018-01-09 | target/xtensa: drop DisasContext::litbase | Max Filippov |
2018-01-09 | target/xtensa: use libisa for instruction decoding | Max Filippov |
2017-12-18 | target/xtensa: switch fsf to libisa | Max Filippov |
2017-12-18 | target/xtensa: switch dc233c to libisa | Max Filippov |
2017-12-18 | target/xtensa: switch dc232b to libisa | Max Filippov |
2017-12-18 | target/xtensa: update import_core.sh script for libisa | Max Filippov |
2017-12-18 | target/xtensa: extract FPU2000 opcode translators | Max Filippov |
2017-12-18 | target/xtensa: extract core opcode translators | Max Filippov |
2017-12-18 | target/xtensa: import libisa source | Max Filippov |
2017-12-18 | target/xtensa: pass actual frame size to the entry helper | Max Filippov |
2017-10-30 | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ... | Peter Maydell |
2017-10-27 | xtensa: cleanup cpu type name composition | Igor Mammedov |
2017-10-27 | Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging | Peter Maydell |
2017-10-25 | disas: Remove unused flags arguments | Richard Henderson |
2017-10-24 | tcg: Initialize cpu_env generically | Richard Henderson |
2017-10-24 | tcg: define tcg_init_ctx and make tcg_ctx a pointer | Emilio G. Cota |
2017-10-24 | tcg: convert tb->cflags reads to tb_cflags(tb) | Emilio G. Cota |
2017-10-24 | qom: Introduce CPUClass.tcg_initialize | Richard Henderson |
2017-10-09 | qom/cpu: move cpu_model null check to cpu_class_by_name() | Philippe Mathieu-Daudé |
2017-09-26 | target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macro | Alistair Francis |
2017-09-06 | target: [tcg] Use a generic enum for DISAS_ values | Lluís Vilanova |
2017-09-01 | xtensa: replace cpu_xtensa_init() with cpu_generic_init() | Igor Mammedov |
2017-07-19 | tcg: Pass generic CPUState to gen_intermediate_code() | Lluís Vilanova |
2017-07-14 | char: add backend hotswap handler | Anton Nefedov |
2017-07-11 | target/xtensa: gdbstub: drop dead return statement | Max Filippov |
2017-06-06 | target/xtensa: handle unknown registers in gdbstub | Max Filippov |
2017-06-06 | target/xtensa: support output to chardev console | Max Filippov |
2017-06-06 | target/xtensa: fix return value of read/write simcalls | Max Filippov |
2017-06-06 | target/xtensa: fix mapping direction in read/write simcalls | Max Filippov |
2017-03-18 | Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into staging | Peter Maydell |
2017-03-11 | target/xtensa: fix semihosting argc/argv implementation | Max Filippov |
2017-03-09 | target/xtensa: hold BQL for interrupt processing | Alex Bennée |
2017-02-23 | target/xtensa: add two missing headers to core import script | Max Filippov |
2017-02-23 | target/xtensa: sim: instantiate local memories | Max Filippov |
2017-02-21 | monitor: Fix crashes when using HMP commands without CPU | Thomas Huth |
2017-01-25 | Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging | Peter Maydell |