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AgeCommit message (Expand)Author
2017-10-30Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2017-10-27xtensa: cleanup cpu type name compositionIgor Mammedov
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell
2017-10-25disas: Remove unused flags argumentsRichard Henderson
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé
2017-09-26target/xtensa: Use the pre-defined MEMTXATTRS_UNSPECIFIED macroAlistair Francis
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova
2017-09-01xtensa: replace cpu_xtensa_init() with cpu_generic_init()Igor Mammedov
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova
2017-07-14char: add backend hotswap handlerAnton Nefedov
2017-07-11target/xtensa: gdbstub: drop dead return statementMax Filippov
2017-06-06target/xtensa: handle unknown registers in gdbstubMax Filippov
2017-06-06target/xtensa: support output to chardev consoleMax Filippov
2017-06-06target/xtensa: fix return value of read/write simcallsMax Filippov
2017-06-06target/xtensa: fix mapping direction in read/write simcallsMax Filippov
2017-03-18Merge remote-tracking branch 'remotes/xtensa/tags/20170317-xtensa' into stagingPeter Maydell
2017-03-11target/xtensa: fix semihosting argc/argv implementationMax Filippov
2017-03-09target/xtensa: hold BQL for interrupt processingAlex Bennée
2017-02-23target/xtensa: add two missing headers to core import scriptMax Filippov
2017-02-23target/xtensa: sim: instantiate local memoriesMax Filippov
2017-02-21monitor: Fix crashes when using HMP commands without CPUThomas Huth
2017-01-25Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into stagingPeter Maydell
2017-01-16target-xtensa: implement RER/WER instructionsMax Filippov
2017-01-15target/xtensa: implement MEMCTL SRMax Filippov
2017-01-15target/xtensa: fix ICACHE/DCACHE options detectionMax Filippov
2017-01-15target/xtensa: don't continue translation after exceptionMax Filippov
2017-01-15target/xtensa: support icountMax Filippov
2017-01-15target/xtensa: refactor CCOUNT/CCOMPAREMax Filippov
2017-01-15target/xtensa: implement RUNSTALLMax Filippov
2017-01-15target/xtensa: add static vectors selectionMax Filippov
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
2017-01-10target-xtensa: Use clrsb helperRichard Henderson
2017-01-10target-xtensa: Use clz opcodeRichard Henderson
2016-12-20Move target-* CPU file into a target/ folderThomas Huth