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2019-05-10target/xtensa: get rid of centralized SR propertiesMax Filippov
SR numbers are not unique: different Xtensa options may reuse SR number for different purposes. Introduce generic rsr/wsr functions and xsr template and use them instead of centralized SR access functions. Change prototypes of specific rsr/wsr functions to match XtensaOpcodeOp and use them instead of centralized SR access functions. Put xtensa option that introduces SR into the second opcode description parameter and use it to test for rsr/wsr/xsr opcode validity. Extract SR and UR names for the xtensa_cpu_dump_state from libisa. Merge SRs and URs in the dump. Register names of used SR/UR in init_libisa and use these names for TCG globals referencing these SR/UR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson
In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
2019-03-21target/xtensa: fix break_dependency for repeated resourcesMax Filippov
break_dependency incorrectly handles the case of dependency on an opcode that references the same register multiple times. E.g. the following instruction is translated incorrectly: { or a2, a3, a3 ; or a3, a2, a2 } This happens because resource indices of both dependency graph nodes are incremented, and a copy for the second instance of the same register in the ending node is not done. Only increment resource index of the ending node of the dependency. Add test. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: implement PREFCTL SRMax Filippov
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial implementation for this SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: prioritize load/store in FLIX bundlesMax Filippov
Load/store opcodes may raise MMU exceptions. Normally exceptions should be checked in priority order before any actual operations, but since MMU exceptions are tightly coupled with actual memory access, there's currently no way to do it. Approximate this behavior by executing all load, then all store, and then all other opcodes in the FLIX bundles. Use opcode dependency mechanism to express ordering. Mark load/store opcodes with XTENSA_OP_{LOAD,STORE} flags. Newer libisa has classifier functions that can tell whether opcode is a load or store, but this information is not available in the existing overlays. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: break circular register dependenciesMax Filippov
Currently topologic opcode sorting stops at the first detected dependency loop. Introduce struct opcode_arg_copy that describes temporary register copy. Scan remaining opcodes searching for dependencies that can be broken, break them by introducing temporary register copies and record them in an array. In case of success create local temporaries and initialize them with current register values. Share single temporary copy between all register users. Delete temporaries after translation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: reorganize access to boolean registersMax Filippov
libisa represents boolean registers b0..b16 as a BR register file and as BR4 and BR8 register groups. Add these register files and use OpcodeArg::{in,out} parameters to access boolean registers in translators. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: reorganize access to MAC16 registersMax Filippov
libisa represents MAC16 registers m0..m3 as an MR register file. Add this register file and reference its registers directly from the translate_mac16. Drop translator parameter that indicates whether opcode argument is in ar or in mr. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: reorganize register handling in translatorsMax Filippov
To support circular register dependencies in FLIX bundles opcode inputs and outputs must be separate and adjustable. Circular dependencies can be broken by making temporary copies of opcode inputs and substituting them into the arguments array instead of the original registers. E.g. the circular register dependency in the following bundle: { mov a2, a3 ; mov a3, a2 } can be resolved by making copy a2' = a2 and substituting it as input argument of the second opcode: { mov a2, a3 ; mov a3, a2' } Change opcode translator prototype to accept OpcodeArg array as argument. For each register argument initialize OpcodeArg::{in,out} with TCGv_* of the respective register. Don't explicitly use cpu_R in the opcode translators, use OpcodeArg::{in,out} instead. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: only rotate window in the retw helperMax Filippov
Move return address calculation and WINDOW_START adjustment out of the retw helper to simplify logic a bit and avoid using registers directly. Pass a0 as a parameter to the helper. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov
Opcodes that modify WINDOW_BASE SR don't have dependency on opcodes that use windowed registers. If such opcodes are combined in a single instruction they may not be correctly ordered. Instead of adding said dependency use temporary register to store changed WINDOW_BASE value and do actual register window rotation as a postprocessing step. Not all opcodes that change WINDOW_BASE need this: retw, rfwo and rfwu are also jump opcodes, so they are guaranteed to be translated last and thus will not affect other opcodes in the same instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: add generic instruction post-processingMax Filippov
Some opcodes may need additional actions at every exit from the translated instruction or may need to amend TB exit slots available to jumps generated for the instruction. Add gen_postprocess function and call it from the gen_jump_slot and from the disas_xtensa_insn. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28target/xtensa: sort FLIX instruction opcodesMax Filippov
Opcodes in different slots may read and write same resources (registers, states). In the absence of resource dependency loops it must be possible to sort opcodes to avoid interference. Record resources used by each opcode in the bundle. Build opcode dependency graph and use topological sort to order its nodes. In case of success translate opcodes in sort order. In case of failure report and raise invalid opcode exception. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: implement wide branches and loopsMax Filippov
FLIX adds branch and loop instruction variants with 15- and 18-bit wide target offset. Implement them as additional names for the ordinary branch/loop opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov
There are opcodes that differ only in encoding or possible range of immediate arguments. Allow multiple names for single opcode translation table entry to reduce code duplication in that case. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov
Requirement for alphabetical opcode sorting in opcode tables is awkward and does not allow sharing implementation between multiple opcodes. Use hash tables to find opcodes by name. Move implementation from the translate.c to the helper.c to its only user and remove declaration from the cpu.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-11target/xtensa: get rid of gen_callw[i]Max Filippov
Merge gen_callwi and gen_callw into their only users, translate_callw and translate_callxw. Extract jump slot adjustment logic into a separate function and use it in gen_jumpi and translate_callw. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-10target/xtensa: don't specify windowed registers manuallyMax Filippov
Use libisa to extract whether opcode uses windowed registers and construct mask based on that. This only leaves special case for the 'entry' opcode, as it needs to probe a register dynamically. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24target/xtensa: fix access to the INTERRUPT SRMax Filippov
INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov
Don't invalidate TB with the end of zero overhead loop when LBEG or LEND change. Instead encode the distance from the start of the page where the TB starts to the LEND in the TB cs_base and generate loopback code when the next PC matches encoded LEND. Distance to a destination within the same page and up to a maximum instruction length into the next page is encoded literally, otherwise it's zero. The distance from LEND to LBEG is also encoded in the cs_base: it's encoded literally when less than 256 or as 0 otherwise. This allows for TB chaining for the loopback branch at the end of a loop for the most common loop sizes. With this change the resulting emulation speed is about 10% higher in softmmu mode on uClibc-ng and LTP tests. Emulation speed in linux user mode is a few percent lower because there's no direct TB chaining between different memory pages. Testing with lower limit on direct TB chaining range shows gradual slowdown to ~15% for the block size of 64 bytes and ~50% for the block size of 32 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-01target/xtensa: extract gen_check_interrupts callMax Filippov
- mark instructions that affect active IRQ level; - put call for gen_check_interrupts right after the instruction translation; when FLIX is enabled it will need to appear before other exits from the TB as well; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: make rsr/wsr helpers return voidMax Filippov
Now that all logic for TB termination is extracted from rsr/wsr their return value is not used and may be dropped. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract unconditional TB termination via slot 0Max Filippov
- mark instructions that require TB termination via slot 0; - put TB termination right after the instruction translation loop, if termination w/o TB linking wasn't requested; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov
Currently we only end TB in icount mode, because access to CCOUNT or write to CCOMPARE are IO operations. Simplify the behaviour a bit and end TB unconditionally. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: change SR number checks to assertionsMax Filippov
Opcode decoding with libisa takes care about range of valid group SRs, like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr implementations into assertions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract unconditional TB terminationMax Filippov
- mark all instructions that exit TB and require dynamic search for the next TB; - put TB termination right after the instruction translation loop; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for division by zeroMax Filippov
- mark quos/quou/rems/remu instructions; - drop parameter 0 from the translate_quou and split translate_remu from it; - put test for division by zero exception right after the coprocessor exception test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov
- add XtensaOpcodeOps::coprocessor with bitmask of coprocessors used by the instruction; - replace coprocessor id parameter of gen_check_cpenable with the bitmask of used coprocessors; - collect coprocessor IDs used by an instruction in the disassembly loop; - put test for coprocessor disabled exception after the alloca test; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for alloca exceptionMax Filippov
- mark movsp instruction; - put test for alloca exception right after the test for window underflow; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for window underflow exceptionMax Filippov
- mark retw and retw.n instructions; - extract window inderflow test from retw helper; - put underflow exception check generation right after the overflow check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov
- add ps.callinc to the TB flags, that allows testing all instructions for window overflow statically; - drop gen_window_check* functions; replace them with get_window_check that accepts bitmask of used registers; - add XtensaOpcodeOps::test_overflow that returns bitmask of implicitly used registers; use it for entry and call{,x}{4,8,12}; - drop window overflow test from the entry helper; - drop parameter 0 from translate_[di]cache and use translate_nop for d/i cache opcodes that don't need memory accessibility check; - add bitmask XtensaOpcodeOps::windowed_register_op that marks opcode arguments that refer to windowed registers; - translate windowed_register_op mask to a mask of actually used registers in the disassembly loop; - add check for window overflow right after the check for debug exception; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for debug exceptionMax Filippov
- mark break and break.n instructions; - collect debug cause bits from parameter 0 of instructions marked for debug exception; - put debug exception check right after syscall check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for syscall instructionMax Filippov
- mark syscall instruction; - put syscall exception check right after privileged exception check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for privileged instructionMax Filippov
- mark privileged instructions; - put single privileged instruction check after disassembly loop; - translate_[di]cache: drop parameter 0, shift parameters one down; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov
- TB flags: add XTENSA_TBFLAG_CWOE that corresponds to the architectural CWOE state; - entry: move CWOE check from the helper to the test_ill_entry; - retw: move CWOE check from the helper to the test_ill_retw; - separate instruction disassembly loop and translation loop; save disassembly results in local array; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov
s32c1i must load and store value with target endianness, not host. This results in an infinite loop in atomic cmpxchg sequences when target endianness doesn't match host endianness. Fixes: 9fb40342d4b3 ("target/xtensa: support MTTCG") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-09-17target/xtensa: fix FPU2000 bugsMax Filippov
- FPU2000 defines rfr and wfr opcodes, not rfr.s and wfr.s; - movcond.s uses incorrect operand in tcg_gen_movcond: in case the condition is not satisfied it must not change its argument 0. Fixes: c04e1692e3aa ("target/xtensa: extract FPU2000 opcode translators") Cc: qemu-stable@nongnu.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Convert to TranslatorOpsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Change gen_intermediate_code dc to pointerRichard Henderson
This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Convert to DisasContextBaseRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURNRichard Henderson
The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov
ISA book documents that the first instruction of zero overhead loop must fit completely into naturally aligned region of an instruction fetch unit size. Check that condition and log a message if it's violated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-06-08target/xtensa: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-id: 20180606152128.449-12-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-21Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-fetch' into ↵Peter Maydell
staging trivial patches for 2018-05-20 # gpg: Signature made Sun 20 May 2018 07:13:20 BST # gpg: using RSA key 701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * remotes/mjt/tags/trivial-patches-fetch: (22 commits) acpi: fix a comment about aml_call0() qapi/net.json: Fix the version number of the "vlan" removal gdbstub: Handle errors in gdb_accept() gdbstub: Use qemu_set_cloexec() replace functions which are only available in glib-2.24 typedefs: Remove PcGuestInfo from qemu/typedefs.h qemu-options: Allow -no-user-config again hw/timer/mt48t59: Fix bit-rotten NVRAM_PRINTF format strings Remove unnecessary variables for function return value trivial: Do not include pci.h if it is not necessary tests: fix tpm-crb tpm-tis tests race hw/ide/ahci: Keep ALLWINNER_AHCI() macro internal qemu-img-cmds.hx: add passive-aggressive note qemu-img: Make documentation between .texi and .hx consistent qemu-img: remove references to GEN_DOCS qemu-img.texi: fix command ordering qemu-img-commands.hx: argument ordering fixups HACKING: document preference for g_new instead of g_malloc qemu-option-trace: -trace enable= is a pattern, not a file slirp/debug: Print IP addresses in human readable form ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-20Remove unnecessary variables for function return valueLaurent Vivier
Re-run Coccinelle script scripts/coccinelle/return_directly.cocci Signed-off-by: Laurent Vivier <lvivier@redhat.com> ppc part Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2018-05-18target/xtensa: Honor CPU_DUMP_FPURichard Henderson
Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
2018-05-10target/xtensa: Use new min/max expandersRichard Henderson
The generic expanders replace nearly identical code in the translator. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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