Age | Commit message (Expand) | Author |
2022-04-06 | Replace TARGET_WORDS_BIGENDIAN | Marc-André Lureau |
2020-08-21 | target/xtensa: add DFPU registers and opcodes | Max Filippov |
2020-08-21 | target/xtensa: add DFPU option | Max Filippov |
2020-08-21 | target/xtensa: implement NMI support | Max Filippov |
2020-05-17 | target/xtensa: fetch HW version from configuration overlay | Max Filippov |
2020-01-06 | target/xtensa: use MPU background map from core configuration | Max Filippov |
2019-05-15 | target/xtensa: implement exclusive access option | Max Filippov |
2019-05-14 | target/xtensa: implement DIWBUI.P opcode | Max Filippov |
2019-05-10 | target/xtensa: implement MPU option | Max Filippov |
2019-05-10 | target/xtensa: add parity/ECC option SRs | Max Filippov |
2019-05-10 | target/xtensa: define IDMA and gather/scatter IRQ types | Max Filippov |
2019-02-18 | target/xtensa: move xtensa_finalize_config to xtensa_core_class_init | Max Filippov |
2019-01-11 | target/xtensa: rework zero overhead loops implementation | Max Filippov |
2018-06-30 | target/xtensa: check zero overhead loop alignment | Max Filippov |
2018-03-13 | target/xtensa: use correct number of registers in gdbstub | Max Filippov |
2018-01-11 | target/xtensa: fix default sysrom/sysram addresses | Max Filippov |
2017-02-23 | target/xtensa: sim: instantiate local memories | Max Filippov |
2017-01-16 | target-xtensa: implement RER/WER instructions | Max Filippov |
2017-01-15 | target/xtensa: implement MEMCTL SR | Max Filippov |
2017-01-15 | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov |
2017-01-15 | target/xtensa: add static vectors selection | Max Filippov |
2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |