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path: root/target/xtensa/cpu.h
AgeCommit message (Expand)Author
2020-01-15target/xtensa: Remove MMU_MODE{0,1,2,3}_SUFFIXRichard Henderson
2020-01-06target/xtensa: fix ps.ring use in MPU configsMax Filippov
2019-09-11target/xtensa: linux-user: add call0 ABI supportMax Filippov
2019-08-20configure: Define target access alignment in configuretony.nguyen@bt.com
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
2019-06-10cpu: Remove CPU_COMMONRichard Henderson
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson
2019-06-10target/xtensa: Use env_cpu, env_archcpuRichard Henderson
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson
2019-06-10cpu: Define ArchCPURichard Henderson
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson
2019-05-21Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell
2019-05-15target/xtensa: implement exclusive access optionMax Filippov
2019-05-15target/xtensa: update list of exception causesMax Filippov
2019-05-14target/xtensa: implement DIWBUI.P opcodeMax Filippov
2019-05-10target/xtensa: implement MPU optionMax Filippov
2019-05-10target/xtensa: add parity/ECC option SRsMax Filippov
2019-05-10target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov
2019-05-10target/xtensa: make internal MMU functions staticMax Filippov
2019-05-10target/xtensa: get rid of centralized SR propertiesMax Filippov
2019-05-10target/xtensa: Convert to CPUClass::tlb_fillRichard Henderson
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster
2019-04-18target: Clean up how the dump_mmu() printMarkus Armbruster
2019-04-18target: Simplify how the TARGET_cpu_list() printMarkus Armbruster
2019-02-28target/xtensa: implement PREFCTL SRMax Filippov
2019-02-28target/xtensa: prioritize load/store in FLIX bundlesMax Filippov
2019-02-28target/xtensa: reorganize register handling in translatorsMax Filippov
2019-02-28target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov
2019-02-28target/xtensa: add generic instruction post-processingMax Filippov
2019-02-28target/xtensa: sort FLIX instruction opcodesMax Filippov
2019-02-18target/xtensa: allow multiple names for single opcodeMax Filippov
2019-02-18target/xtensa: don't require opcode table sortingMax Filippov
2019-02-18target/xtensa: move xtensa_finalize_config to xtensa_core_class_initMax Filippov
2019-02-10target/xtensa: don't specify windowed registers manuallyMax Filippov
2019-01-28target/xtensa: expose core runstall as an IRQ lineMax Filippov
2019-01-28target/xtensa: rearrange access to external interruptsMax Filippov
2019-01-28target/xtensa: drop function xtensa_timer_irqMax Filippov
2019-01-11target/xtensa: rework zero overhead loops implementationMax Filippov
2018-10-01target/xtensa: extract test for cpdisabled exceptionMax Filippov
2018-10-01target/xtensa: extract test for window overflow exceptionMax Filippov
2018-10-01target/xtensa: extract test for an illegal instructionMax Filippov
2018-09-17target/xtensa: convert to do_transaction_failedMax Filippov
2018-08-19target/xtensa: clean up gdbstub register handlingMax Filippov
2018-06-30target/xtensa: check zero overhead loop alignmentMax Filippov
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov
2018-03-16target/xtensa: add linux-user supportMax Filippov
2018-03-13target/xtensa: support MTTCGMax Filippov