| Age | Commit message (Expand) | Author |
|---|
| 2017-09-01 | sparc: embed sparc_def_t into CPUSPARCState | Igor Mammedov |
| 2017-07-19 | tcg: Pass generic CPUState to gen_intermediate_code() | Lluís Vilanova |
| 2017-07-19 | target/sparc: optimize gen_op_mulscc() using deposit op | Philippe Mathieu-Daudé |
| 2017-07-19 | target/sparc: optimize various functions using extract op | Philippe Mathieu-Daudé |
| 2017-03-02 | target/sparc: Restore ldstub of odd asis | Richard Henderson |
| 2017-01-18 | target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs | Artyom Tarasenko |
| 2017-01-18 | target-sparc: use direct address translation in hyperprivileged mode | Artyom Tarasenko |
| 2017-01-18 | target-sparc: fix immediate UA2005 traps | Artyom Tarasenko |
| 2017-01-18 | target-sparc: implement UA2005 rdhpstate and wrhpstate instructions | Artyom Tarasenko |
| 2017-01-18 | target-sparc: implement UA2005 GL register | Artyom Tarasenko |
| 2017-01-18 | target-sparc: hypervisor mode takes over nucleus mode | Artyom Tarasenko |
| 2017-01-18 | target-sparc: implement UltraSPARC-T1 Strand status ASR | Artyom Tarasenko |
| 2017-01-18 | target-sparc: store cpu super- and hypervisor flags in TB | Artyom Tarasenko |
| 2017-01-10 | target-sparc: Use ctpop helper | Richard Henderson |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth |
