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2019-03-11s390x/tcg: Implement VECTOR UNPACK *David Hildenbrand
Combine all variant in a single handler. As source and destination have different element sizes, we can't use gvec expansion. Expand manually. Also watch out for overlapping source and destination registers. Use a safe evaluation order depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-33-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE WITH LENGTHDavid Hildenbrand
Very similar to VECTOR LOAD WITH LENGTH, just the opposite direction. Properly probe write access before modifying memory. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-32-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE MULTIPLEDavid Hildenbrand
Similar to VECTOR LOAD MULTIPLE, just the opposite direction. Probe write access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-31-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STORE ELEMENTDavid Hildenbrand
As we only store one element, there is nothing to consider regarding exceptions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-30-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR STOREDavid Hildenbrand
Properly probe the whole access first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-29-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SIGN EXTEND TO DOUBLEWORDDavid Hildenbrand
Load both elements signed and store them into the two 64 bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-27-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SELECTDavid Hildenbrand
Provide an implementation based on i64 and on real host vectors. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-26-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR SCATTER ELEMENTDavid Hildenbrand
Similar to VECTOR GATHER ELEMENT, but the other direction. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-25-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR REPLICATE IMMEDIATEDavid Hildenbrand
Like VECTOR REPLICATE, but the element to be replicated comes from an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-24-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR REPLICATEDavid Hildenbrand
Replicate via the special gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-23-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PERMUTE DOUBLEWORD IMMEDIATEDavid Hildenbrand
Read the whole input before modifying the destination vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-22-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PERMUTEDavid Hildenbrand
Take care of overlying inputs and outputs by using a temporary vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-21-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR PACK *David Hildenbrand
This is a big one. Luckily we only have a limited set of such nasty instructions. We'll implement all variants with helpers, except when sources and the destination don't overlap for VECTOR PACK. Provide different helpers when the cc is to be modified. We'll return the cc then via env->cc_op. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-20-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR MERGE (HIGH|LOW)David Hildenbrand
We cannot use gvec expansion as source and destination elements are have different element numbers. So we'll expand using a fancy loop. Also, we have to take care of overlapping source and destination registers, therefore use a safe evaluation irder depending on the operation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD WITH LENGTHDavid Hildenbrand
We can reuse the helper introduced along with VECTOR LOAD TO BLOCK BOUNDARY. We just have to take care of converting the highest index into a length. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD VR FROM GRS DISJOINTDavid Hildenbrand
Fairly easy, just load from to gprs into a single vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD VR ELEMENT FROM GRDavid Hildenbrand
Very similar to VECTOR LOAD GR FROM VR ELEMENT, just the opposite direction. Also provide a fast path in case we don't care about the register content. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD TO BLOCK BOUNDARYDavid Hildenbrand
Very similar to LOAD COUNT TO BLOCK BOUNDARY, but instead of only calculating, the actual vector is loaded. Use a temporary vector to not modify the real vector on exceptions. Initialize that one to zero, to not leak any data. Provide a fast path if we're loading a full vector. As we don't have gvec ool handlers for single vectors, just calculate the vector address manually. We can reuse the helper later on for VECTOR LOAD WITH LENGTH. In fact, we are going to name it "vll" right from the beginning, because that's a better match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD MULTIPLEDavid Hildenbrand
Try to load the last element first. Access to the first element will be checked afterwards. This way, we can guarantee that the vector is not modified before we checked for all possible exceptions. (16 vectors cannot cross more than two pages) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD LOGICAL ELEMENT AND ZERODavid Hildenbrand
Fairly easy, zero out the vector before we load the desired element. Load the element before touching the vector. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD GR FROM VR ELEMENTDavid Hildenbrand
To avoid an helper, we have to do the actual calculation of the element address (offset in cpu_env + cpu_env) manually. Factor that out into get_vec_element_ptr_i64(). The same logic will be reused for "VECTOR LOAD VR ELEMENT FROM GR". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENT IMMEDIATEDavid Hildenbrand
Take care of properly sign-extending the immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD ELEMENTDavid Hildenbrand
Fairly easy, load with desired size and store it into the right element. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOAD AND REPLICATEDavid Hildenbrand
We can use tcg_gen_gvec_dup_i64() to carry out the duplication. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR LOADDavid Hildenbrand
When loading from memory, load both elements into temps first before modifying the target vector Loading with strange alingment from the end of the address space will not properly wrap, we can ignore that for now. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR GENERATE MASKDavid Hildenbrand
Add gen_gvec_dupi() for handling duplication of immediates, so it can be reused later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR GENERATE BYTE MASKDavid Hildenbrand
Let's optimize it for the common cases (setting a vector to zero or all ones) - courtesy of Richard. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-11s390x/tcg: Implement VECTOR GATHER ELEMENTDavid Hildenbrand
Let's start with a more involved one, but it is the first in the list of vector support instructions (introduced with the vector facility). Good thing is, we need a lot of basic infrastructure for this. Reading and writing vector elements as well as checking element validity. All vector instruction related translation functions will reside in translate_vx.inc.c, to be included in translate.c - similar to how other architectures handle it. While at it, directly add some documentation (which contains parts about things added in follow-up patches, but splitting this up does not make too much sense). Also add ES_* defines heavily used later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190307121539.12842-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement rounding mode and XxC for LOAD ROUNDEDDavid Hildenbrand
With the floating-point extension facility, LOAD ROUNDED has a rounding mode specification and the inexact-exception control (XxC). Handle them just like e.g. LOAD FP INTEGER. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Check for exceptions in SET BFP ROUNDING MODEDavid Hildenbrand
Let's split handling of BFP/DFP rounding mode configuration. Also, let's not reuse the sfpc handler, use a separate handler so we can properly check for specification exceptions for SRNMB. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190218122710.23639-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement LOAD COUNT TO BLOCK BOUNDARYDavid Hildenbrand
Use a new CC helper to calculate the CC lazily if needed. While the PoP mentions that "A 32-bit unsigned binary integer" is placed into the first operand, there is no word telling that the other 32 bits (high part) are left untouched. Maybe the other 32-bit are unpredictable. So store 64 bit for now. Bit magic courtesy of Richard. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-8-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-03-04s390x/tcg: Implement LOAD LENGTHENED short HFP to long HFPDavid Hildenbrand
Nice trick to load a 32 bit value into vector element 0 (32 bit element size) from memory, zeroing out element1. The short HFP to long HFP conversion really only is a shift. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190225200318.16102-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-18target/s390x: Implement STCK et al for CONFIG_USER_ONLYRichard Henderson
This is a non-privileged instruction that was only implemented for system mode. However, the stck instruction is used by glibc, so this was causing SIGILL for programs run under debian stretch. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20190212053044.29015-3-richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-02-04s390x/tcg: Don't model FP registers as globalsDavid Hildenbrand
As floating point registers overlay some vector registers and we want to make use of the general tcg_gvec infrastructure that assumes vectors are not stored in globals but in memory, don't model floating point registers as globals anymore. This is then similar to how arm handles it. Reading/writing a floating point register means reading/writing memory now. Break up ugly in2_x2() handling that modifies both, in1 and in2 into in2_x2l and in2_x2h. This makes things more readable. Also, in1_x1() is ugly as it touches out/out2, get rid of that and use prep_x1() instead. As we are no longer able to use the original global variables for out/out2, we have to use new temporary variables and write from them to the target registers using wout_ helpers. E.g. an instruction that reads and writes x1 will use - prep_x1 to get the values into out/out2 - wout_x1 to write the values from out/out2 This special handling is needed for x1 as it is often used along with other inputs, so in1/in2 is already used. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190204154406.16122-1-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: handle privileged instructions via flagsDavid Hildenbrand
Let's check this also at a central place. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-8-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: add instruction flags for floating point instructionsDavid Hildenbrand
These flags allow us to later on detect if a DATA program interrupt is to be injected, and which DXC (1,2,3) is to be used. Interestingly, some support FP instructions are considered as HFP instructions (I assume simply because they were available very early). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-6-david@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-04s390x/tcg: support flags for instructionsDavid Hildenbrand
Storing flags for instructions allows us to efficiently verify certain properties at a central point. Examples might later be handling if AFP is disabled in CR0, we are not in problem state, or if vector instructions are disabled in CR0. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180927130303.12236-5-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28target/s390x: add BAL and BALR instructionsPavel Zbitskiy
These instructions are provided for compatibility purposes and are used only by old software, in the new code BAS and BASR are preferred. The difference between the old and new instruction exists only in the 24-bit mode. In addition, fix BAS polluting high 32 bits of the first operand in 24- and 31-bit addressing modes. Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com> Message-Id: <20180821025104.19604-3-pavel.zbitskiy@gmail.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-07-02s390x/tcg: implement SET CLOCKDavid Hildenbrand
This allows a guest to change its TOD. We already take care of updating all CKC timers from within S390TODClass. Use MO_ALIGN to load the operand manually - this will properly trigger a SPECIFICATION exception. Acked-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180627134410.4901-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-26s390x/tcg: add various alignment checksDavid Hildenbrand
Let's add proper alignment checks for a handful of instructions that require a SPECIFICATION exception in case alignment is violated. Introduce new wout/in functions. As we are right now only using them for privileged instructions, we have to add ugly ifdefs to silence compilers. Convert STORE CPU ID right away to make use of the wout function. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180215103822.15179-1-david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: wire up pci instructionsCornelia Huck
On s390x, pci support is implemented via a set of instructions (no mmio). Unfortunately, none of them are documented in the PoP; the code is based upon the existing implementation for KVM and the Linux zpci driver. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-02-09s390x/tcg: implement TEST PENDING INTERRUPTIONDavid Hildenbrand
Use s390_cpu_virt_mem_write() so we can actually revert what we did (re-inject the dequeued IO interrupt). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20180129125623.21729-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: implement extract-CPU-time facilityDavid Hildenbrand
It only provides the EXTRACT CPU TIME instruction. We can reuse the stpt helper, which calculates the CPU timer value. As the instruction is not privileged, but we don't have a CPU timer value in case of linux user, we simply reuse cpu_get_host_ticks() to produce some descending value. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: Implement SIGNAL ADAPTER instructionDavid Hildenbrand
KVM suppresses SIGA, setting cc=3. Let's do the same for TCG, so we're at least equal. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: Implement STORE CHANNEL PATH STATUSDavid Hildenbrand
Just like KVM does, we should suppress this instruction: When this instruction is not provided, it is checked for privileged operation exception and the instruction is suppressed by the machine Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up SET CHANNEL MONITORDavid Hildenbrand
Let's just wire it up like KVM. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up SET ADDRESS LIMITDavid Hildenbrand
Let's handle it just like KVM: Depending on the model, this instruction may not be provided. When this instruction is not provided, it is checked for operand exception and privileged-opera- tion exception, and then is suppressed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-9-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: implement Interlocked-Access Facility 2David Hildenbrand
With this facility, OI/OIY, NI/NIY and XI/XIY are atomic. All operate on one byte (MO_UB). Emulate old behavior. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: ASI/ASGI/ALSI/ALSGI are atomic with Interlocked-acccess facility 1David Hildenbrand
The semantics of ASI/ASGI/ALSI/ALSGI changed. Let's implement them just like LOAD AND ADD, so they are atomic. Emulate old behavior. This fixes random crashes when booting a Linux kernel compiled for z196+ with SMP + MTTCG. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-7-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-12-14s390x/tcg: wire up STORE CHANNEL REPORT WORDDavid Hildenbrand
CRW machine check handling requires STCRW. So let's wire it up. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20171208160207.26494-6-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>