slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-09-28	Merge tag 'pull-request-2024-09-25' of https://gitlab.com/thuth/qemu into sta...	Peter Maydell
2024-09-24	target/riscv: remove break after g_assert_not_reached()	Pierrick Bouvier
2024-09-20	license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later	Philippe Mathieu-Daudé
2024-09-13	target/riscv: Remove the deprecated 'any' CPU type	Philippe Mathieu-Daudé
2024-08-06	target/riscv: Add asserts for out-of-bound access	Atish Patra
2024-08-06	target/riscv: Relax fld alignment requirement	LIU Zhiwei
2024-08-06	target/riscv: Add MXLEN check for F/D/Q applies to zama16b	LIU Zhiwei
2024-08-06	target/riscv: Remove redundant insn length check for zama16b	LIU Zhiwei
2024-07-23	Merge tag 'pull-tcg-20240723' of https://gitlab.com/rth7680/qemu into staging	Richard Henderson
2024-07-23	target/riscv: Simplify probing in vext_ldff	Richard Henderson
2024-07-22	target/riscv: Restrict semihosting to TCG	Philippe Mathieu-Daudé
2024-07-18	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	Yu-Ming Chang
2024-07-18	target/riscv: Expose the Smcntrpmf config	Atish Patra
2024-07-18	target/riscv: Do not setup pmu timer if OF is disabled	Atish Patra
2024-07-18	target/riscv: More accurately model priv mode filtering.	Rajnesh Kanwal
2024-07-18	target/riscv: Start counters from both mhpmcounter and mcountinhibit	Rajnesh Kanwal
2024-07-18	target/riscv: Enforce WARL behavior for scounteren/hcounteren	Atish Patra
2024-07-18	target/riscv: Save counter values during countinhibit update	Atish Patra
2024-07-18	target/riscv: Implement privilege mode filtering for cycle/instret	Atish Patra
2024-07-18	target/riscv: Only set INH fields if priv mode is available	Atish Patra
2024-07-18	target/riscv: Add cycle & instret privilege mode filtering support	Kaiwen Xue
2024-07-18	target/riscv: Add cycle & instret privilege mode filtering definitions	Kaiwen Xue
2024-07-18	target/riscv: Add cycle & instret privilege mode filtering properties	Kaiwen Xue
2024-07-18	target/riscv: Fix the predicate functions for mhpmeventhX CSRs	Atish Patra
2024-07-18	target/riscv: Combine set_mode and set_virt functions.	Rajnesh Kanwal
2024-07-18	target/riscv/kvm: update KVM regs to Linux 6.10-rc5	Daniel Henrique Barboza
2024-07-18	target/riscv: Validate the mode in write_vstvec	Jiayi Li
2024-07-18	target/riscv: Expose zabha extension as a cpu property	LIU Zhiwei
2024-07-18	target/riscv: Add amocas.[b\|h] for Zabha	LIU Zhiwei
2024-07-18	target/riscv: Move gen_cmpxchg before adding amocas.[b\|h]	LIU Zhiwei
2024-07-18	target/riscv: Add AMO instructions for Zabha	LIU Zhiwei
2024-07-18	target/riscv: Move gen_amo before implement Zabha	LIU Zhiwei
2024-07-18	target/riscv: Support Zama16b extension	LIU Zhiwei
2024-07-18	target/riscv: Add zcmop extension	LIU Zhiwei
2024-07-18	target/riscv: Add zimop extension	LIU Zhiwei
2024-07-11	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	Peter Maydell
2024-06-27	target/riscv: Apply modularized matching conditions for icount trigger	Alvin Chang
2024-06-27	target/riscv: Apply modularized matching conditions for watchpoint	Alvin Chang
2024-06-27	target/riscv: Add functions for common matching conditions of trigger	Alvin Chang
2024-06-26	target/riscv: Remove extension auto-update check statements	Frank Chang
2024-06-26	target/riscv: Add Zc extension implied rule	Frank Chang
2024-06-26	target/riscv: Add multi extension implied rules	Frank Chang
2024-06-26	target/riscv: Add MISA extension implied rules	Frank Chang
2024-06-26	target/riscv: Introduce extension implied rule helpers	Frank Chang
2024-06-26	target/riscv: Introduce extension implied rules definition	Frank Chang
2024-06-26	target/riscv: fix instructions count handling in icount mode	Clément Léger
2024-06-26	target/riscv: Fix froundnx.h nanbox check	Branislav Brzak
2024-06-26	target/riscv: Support the version for ss1p13	Fea.Wang
2024-06-26	target/riscv: Reserve exception codes for sw-check and hw-err	Fea.Wang
2024-06-26	target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32	Fea.Wang