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AgeCommit message (Expand)Author
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson
2024-01-19target/riscv: Rename tcg_cpu_FOO() to include 'riscv'Philippe Mathieu-Daudé
2024-01-10target/riscv: Ensure mideleg is set correctly on resetAlistair Francis
2024-01-10target/riscv: Don't adjust vscause for exceptionsAlistair Francis
2024-01-10target/riscv: Assert that the CSR numbers will be correctAlistair Francis
2024-01-10target/riscv: pmp: Ignore writes when RW=01 and MML=0Ivan Klokov
2024-01-10target/riscv/kvm: add RVV and Vector CSR regsDaniel Henrique Barboza
2024-01-10target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()Daniel Henrique Barboza
2024-01-10target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...Yong-Xuan Wang
2024-01-10target/riscv: add rva22s64 cpuDaniel Henrique Barboza
2024-01-10target/riscv: add RVA22S64 profileDaniel Henrique Barboza
2024-01-10target/riscv: add 'parent' in profile descriptionDaniel Henrique Barboza
2024-01-10target/riscv: add satp_mode profile supportDaniel Henrique Barboza
2024-01-10target/riscv/cpu.c: add riscv_cpu_is_32bit()Daniel Henrique Barboza
2024-01-10target/riscv/cpu.c: finalize satp_mode earlierDaniel Henrique Barboza
2024-01-10target/riscv: add priv ver restriction to profilesDaniel Henrique Barboza
2024-01-10target/riscv: implement svadeDaniel Henrique Barboza
2024-01-10target/riscv: add 'rva22u64' CPUDaniel Henrique Barboza
2024-01-10riscv-qmp-cmds.c: add profile flags in cpu-model-expansionDaniel Henrique Barboza
2024-01-10target/riscv/tcg: validate profiles during finalizeDaniel Henrique Barboza
2024-01-10target/riscv/tcg: honor user choice for G MISA bitsDaniel Henrique Barboza
2024-01-10target/riscv/tcg: add hash table insert helpersDaniel Henrique Barboza
2024-01-10target/riscv/tcg: handle profile MISA bitsDaniel Henrique Barboza
2024-01-10target/riscv/tcg: add riscv_cpu_write_misa_bit()Daniel Henrique Barboza
2024-01-10target/riscv/tcg: add MISA user options hashDaniel Henrique Barboza
2024-01-10target/riscv/tcg: add user flag for profile supportDaniel Henrique Barboza
2024-01-10target/riscv/kvm: add 'rva22u64' flag as unavailableDaniel Henrique Barboza
2024-01-10target/riscv: add rva22u64 profile definitionDaniel Henrique Barboza
2024-01-10riscv-qmp-cmds.c: expose named features in cpu_model_expansionDaniel Henrique Barboza
2024-01-10target/riscv/tcg: add 'zic64b' supportDaniel Henrique Barboza
2024-01-10target/riscv: add zicbop extension flagDaniel Henrique Barboza
2024-01-10target/riscv: add rv64i CPUDaniel Henrique Barboza
2024-01-10target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza
2024-01-10target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza
2024-01-10target/riscv: create TYPE_RISCV_VENDOR_CPUDaniel Henrique Barboza
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li
2024-01-10target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()Daniel Henrique Barboza
2024-01-10target/riscv/kvm: add RISCV_CONFIG_REG()Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change timer regs size to u64Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32Daniel Henrique Barboza
2024-01-10target/riscv/cpu.c: fix machine IDs gettersDaniel Henrique Barboza
2024-01-10target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei
2024-01-10target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei
2024-01-10target/riscv: The whole vector register move instructions depend on vsewMax Chou
2024-01-10target/riscv: Add vill check for whole vector register move instructionsMax Chou
2024-01-08qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARDStefan Hajnoczi
2024-01-05target/riscv: Fix mcycle/minstret increment behaviorXu Lu
2024-01-05target: Use generic cpu_model_from_type()Gavin Shan
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