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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2021-05-02
hw: Do not include qemu/log.h if it is not necessary
Thomas Huth
2021-03-22
target/riscv: Prevent lost illegal instruction exceptions
Georg Kotheimer
2021-03-22
target/riscv: Add proper two-stage lookup exception detection
Georg Kotheimer
2021-03-22
target/riscv: Fix read and write accesses to vsip and vsie
Georg Kotheimer
2021-03-22
target/riscv: Use background registers also for MSTATUS_MPV
Georg Kotheimer
2021-03-22
target/riscv: Make VSTIP and VSEIP read-only in hip
Georg Kotheimer
2021-03-22
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Georg Kotheimer
2021-03-22
target/riscv: flush TLB pages if PMP permission has been changed
Jim Shu
2021-03-22
target/riscv: add log of PMP permission checking
Jim Shu
2021-03-22
target/riscv: propagate PMP permission to TLB page
Jim Shu
2021-03-22
target/riscv: fix vs() to return proper error code
Frank Chang
2021-03-11
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...
Peter Maydell
2021-03-10
semihosting: Move include/hw/semihosting/ -> include/semihosting/
Philippe Mathieu-Daudé
2021-03-09
Various spelling fixes
Michael Tokarev
2021-03-04
target-riscv: support QMP dump-guest-memory
Yifei Jiang
2021-03-04
target/riscv: Declare csr_ops[] with a known size
Bin Meng
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
2021-02-05
cpu: Move synchronize_from_tb() to tcg_ops
Eduardo Habkost
2021-02-05
target/riscv: remove CONFIG_TCG, as it is always TCG
Claudio Fontana
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
2021-01-18
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...
Peter Maydell
2021-01-18
riscv: Add semihosting support
Keith Packard
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
2021-01-16
target/riscv: Add CSR name in the CSR function table
Bin Meng
2021-01-16
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Bin Meng
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
2021-01-07
tcg: Make tb arg to synchronize_from_tb const
Richard Henderson
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
2020-12-17
target/riscv: csr: Remove compile time XLEN checks
Alistair Francis
2020-12-17
target/riscv: cpu_helper: Remove compile time XLEN checks
Alistair Francis
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
2020-12-17
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
2020-12-17
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Alistair Francis
2020-12-17
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alex Richardson
2020-12-17
target/riscv: Fix the bug of HLVX/HLV/HSV
Yifei Jiang
2020-11-13
hmp: Pass monitor to mon_get_cpu_env()
Kevin Wolf
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
2020-11-09
target/riscv: Add a virtualised MMU Mode
Alistair Francis
2020-11-03
target/riscv/csr.c : add space before the open parenthesis '('
Xinhao Zhang
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