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AgeCommit message (Expand)Author
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
2020-09-18target/riscv: Set instance_align on RISCVCPU TypeInfoRichard Henderson
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell
2020-09-11Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng
2020-09-09target/riscv: cpu: Add a new 'resetvec' propertyBin Meng
2020-09-09target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang
2020-09-09trace-events: Fix attribution of trace points to sourceMarkus Armbruster
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-08-28softfloat: Implement the full set of comparisons for float16Kito Cheng
2020-08-25target/riscv: Support the Virtual Instruction faultAlistair Francis
2020-08-25target/riscv: Return the exception from invalid CSR accessesAlistair Francis
2020-08-25target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis
2020-08-25target/riscv: Only support little endian guestsAlistair Francis
2020-08-25target/riscv: Only support a single VSXL lengthAlistair Francis
2020-08-25target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis
2020-08-25target/riscv: Update the Hypervisor trap return/entryAlistair Francis
2020-08-25target/riscv: Fix the interrupt cause codeAlistair Francis
2020-08-25target/riscv: Convert MSTATUS MTL to GVAAlistair Francis
2020-08-25target/riscv: Don't allow guest to write to htinstAlistair Francis
2020-08-25target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructionsAlistair Francis
2020-08-25target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis
2020-08-25target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis
2020-08-21target/riscv: Change the TLB page size depends on PMP entries.Zong Li
2020-08-21target/riscv: Fix the translation of physical addressZong Li
2020-08-21riscv: Fix bug in setting pmpcfg CSR for RISCV64Hou Weiying
2020-08-21target/riscv: check before allocating TCG tempsLIU Zhiwei
2020-08-21target/riscv: Clean up fmv.w.xLIU Zhiwei
2020-08-21target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Check nanboxed inputs to fp helpersRichard Henderson
2020-08-21target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson
2020-08-21target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson
2020-08-21target/riscv: Generate nanboxed results from fp helpersRichard Henderson
2020-08-21meson: targetPaolo Bonzini
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-08-21trace: switch position of headers to what Meson requiresPaolo Bonzini
2020-08-05target/riscv/vector_helper: Fix build on 32-bit big endian hostsThomas Huth
2020-07-22target/riscv: Fix the range of pmpcfg of CSR funcion tableZong Li
2020-07-22target/riscv: fix vector index load/store constraintsLIU Zhiwei
2020-07-22target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei
2020-07-13target/riscv: Fix pmp NA4 implementationAlexandre Mergnat
2020-07-13target/riscv: fix vill bit index in vtype registerFrank Chang
2020-07-13target/riscv: fix return value of do_opivx_widen()Frank Chang
2020-07-13target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang
2020-07-13target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang
2020-07-02target/riscv: configure and turn on vector extension from command lineLIU Zhiwei
2020-07-02target/riscv: vector compress instructionLIU Zhiwei
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