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AgeCommit message (Expand)Author
2024-01-10target/riscv/tcg: update priv_ver on user_set extensionsDaniel Henrique Barboza
2024-01-10target/riscv/tcg: do not use "!generic" CPU checksDaniel Henrique Barboza
2024-01-10target/riscv: create TYPE_RISCV_VENDOR_CPUDaniel Henrique Barboza
2024-01-10target/riscv: Add support for Zacas extensionWeiwei Li
2024-01-10target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()Daniel Henrique Barboza
2024-01-10target/riscv/kvm: add RISCV_CONFIG_REG()Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change timer regs size to u64Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64Daniel Henrique Barboza
2024-01-10target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32Daniel Henrique Barboza
2024-01-10target/riscv/cpu.c: fix machine IDs gettersDaniel Henrique Barboza
2024-01-10target/riscv/pmp: Use hwaddr instead of target_ulong for RV32Ivan Klokov
2024-01-10target/riscv: Not allow write mstatus_vs without RVVLIU Zhiwei
2024-01-10target/riscv: Fix th.dcache.cval1 priviledge checkLIU Zhiwei
2024-01-10target/riscv: The whole vector register move instructions depend on vsewMax Chou
2024-01-10target/riscv: Add vill check for whole vector register move instructionsMax Chou
2024-01-08qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARDStefan Hajnoczi
2024-01-05target/riscv: Fix mcycle/minstret increment behaviorXu Lu
2024-01-05target: Use generic cpu_model_from_type()Gavin Shan
2024-01-05target/riscv: Use generic cpu_list()Gavin Shan
2024-01-05cpu: Call object_class_dynamic_cast() once in cpu_class_by_name()Philippe Mathieu-Daudé
2023-12-29target/riscv: Constify VMState in machine.cRichard Henderson
2023-12-23target/riscv/kvm: do not use non-portable strerrorname_np()Natanael Copa
2023-12-04target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csrDaniel Henrique Barboza
2023-11-22target/riscv/cpu_helper.c: Fix mxr bit behaviorIvan Klokov
2023-11-22target/riscv/cpu_helper.c: Invalid exception on MMU translation stageIvan Klokov
2023-11-22target/riscv: don't verify ISA compatibility for zicntr and zihpmClément Chigot
2023-11-15target/riscv/cpu.h: spelling fix: separatlyMichael Tokarev
2023-11-07hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()Philippe Mathieu-Daudé
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé
2023-11-07target/riscv: Use env_archcpu() in [check_]nanbox()Philippe Mathieu-Daudé
2023-11-07target/riscv: Move TYPE_RISCV_CPU_BASE definition to 'cpu.h'Philippe Mathieu-Daudé
2023-11-07target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h'Philippe Mathieu-Daudé
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé
2023-11-07target/riscv: Add "pmu-mask" property to replace "pmu-num"Rob Bradford
2023-11-07target/riscv: Use existing PMU counter mask in FDT generationRob Bradford
2023-11-07target/riscv: Don't assume PMU counters are continuousRob Bradford
2023-11-07target/riscv: Propagate error from PMU setupRob Bradford
2023-11-07target/riscv: cpu: Set the OpenTitan priv to 1.12.0Alistair Francis
2023-11-07target/riscv: Move vector crypto extensions to riscv_cpu_extensionsMax Chou
2023-11-07target/riscv: Expose Zvks[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvks[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkn[c|g] extnesion propertiesMax Chou
2023-11-07target/riscv: Add cfg properties for Zvkn[c|g] extensionsMax Chou
2023-11-07target/riscv: Expose Zvkb extension propertyMax Chou
2023-11-07target/riscv: Replace Zvbb checking by ZvkbMax Chou
2023-11-07target/riscv: Add cfg property for Zvkb extensionMax Chou
2023-11-07target/riscv: Expose Zvkt extension propertyMax Chou
2023-11-07target/riscv: Add cfg property for Zvkt extensionMax Chou
2023-11-07target/riscv: correct csr_ops[CSR_MSECCFG]Heinrich Schuchardt
2023-11-07target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapotDaniel Henrique Barboza
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