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AgeCommit message (Expand)Author
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li
2023-05-05target/riscv: Fix the mstatus.MPP value after executing MRETWeiwei Li
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li
2023-05-05target/riscv: Fix format for commentsWeiwei Li
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
2023-05-05target/riscv: Add support for ZceWeiwei Li
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
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