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2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li
PMP entries before (including) the matched PMP entry may only cover partial of the TLB page, and this may split the page into regions with different permissions. Such as for PMP0 (0x80000008~0x8000000F, R) and PMP1 (0x80000000~ 0x80000FFF, RWX), write access to 0x80000000 will match PMP1. However we cannot cache the translation result in the TLB since this will make the write access to 0x80000008 bypass the check of PMP0. So we should check all of them instead of the matched PMP entry in pmp_get_tlb_size() and set the tlb_size to 1 in this case. Set tlb_size to TARGET_PAGE_SIZE if PMP is not support or there is no PMP rules. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517091519.34439-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env->misa_ext |= RVI | RVM | RVA | RVF | RVD; env->misa_ext_mask = env->misa_ext; This works fine for realize() time but this can potentially overwrite env->misa_ext_mask if we reutilize the function for write_misa(). Instead of doing misa_ext_mask = misa_ext, sum up the RVG extensions in misa_ext_mask as well. This won't change realize() time behavior (misa_ext_mask will be == misa_ext) and will ensure that write_misa() won't change misa_ext_mask by accident. After that, rewrite write_misa() to work as follows: - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - suppress RVC if the next insn isn't aligned; - disable RVG if any of RVG dependencies are being disabled by the user; - assign env->misa_ext and run riscv_cpu_validate_set_extensions(). On error, rollback env->misa_ext to its original value, logging a GUEST_ERROR to inform the user about the failed write; - handle RVF and MSTATUS_FS and continue as usual. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230517135714.211809-12-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza
There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza
Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza
We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv version is higher than the priv version of C/F/D. So if we use check for them instead of check for C/F/D totally, it will trigger new problem when we try to disable the extensions based on the configured priv version. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on ↵Weiwei Li
priv version Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their super extensions can simplify the extension related check. However, they may have higher priv version than their super extensions. So we should mask them in the isa_string based on priv version to make them invisible to user if the specified priv version is lower than their minimal priv version. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza
The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza
This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza
The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230517135714.211809-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li
Zc* extensions (version 1.0) are ratified. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230510030040.20528-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv/vector_helper.c: skip set tail when vta is zeroDaniel Henrique Barboza
The function is a no-op if 'vta' is zero but we're still doing a lot of stuff in this function regardless. vext_set_elems_1s() will ignore every single time (since vta is zero) and we just wasted time. Skip it altogether in this case. Aside from the code simplification there's a noticeable emulation performance gain by doing it. For a regular C binary that does a vectors operation like this: ======= #define SZ 10000000 int main () { int *a = malloc (SZ * sizeof (int)); int *b = malloc (SZ * sizeof (int)); int *c = malloc (SZ * sizeof (int)); for (int i = 0; i < SZ; i++) c[i] = a[i] + b[i]; return c[SZ - 1]; } ======= Emulating it with qemu-riscv64 and RVV takes ~0.3 sec: $ time ~/work/qemu/build/qemu-riscv64 \ -cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out real 0m0.303s user 0m0.281s sys 0m0.023s With this skip we take ~0.275 sec: $ time ~/work/qemu/build/qemu-riscv64 \ -cpu rv64,debug=false,vext_spec=v1.0,v=true,vlen=128 ./foo.out real 0m0.274s user 0m0.252s sys 0m0.019s This performance gain adds up fast when executing heavy benchmarks like SPEC. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230427205708.246679-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson
Move a use of TARGET_LONG_BITS out of tcg/tcg.h. Include the new file only where required. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board. CPU specs and general information can be found here: https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/ Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
As per the specification, in 64-bit, if any of the pte reserved bits 60-54 is set an exception should be triggered (see 4.4.1, "Addressing and Memory Protection"). In addition, we must check the napot/pbmt bits are not set if those extensions are not active. Reported-by: Andrea Parri <andrea@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230420150220.60919-1-alexghiti@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova
Before changing the flow check for sv39/48/57. According to specification (for Supervisor mode): Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages. Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur. Likewise for Sv48 and Sv57. So the high bits are equal to bit 38 for sv39. According to specification (for Hypervisor mode): For Sv39x4, address bits of the guest physical address 63:41 must all be zeros, or else a guest-page-fault exception occurs. Likewise for Sv48x4 and Sv57x4. For Sv48x4 address bits 63:50 must all be zeros, or else a guest-page-fault exception occurs. For Sv57x4 address bits 63:59 must all be zeros, or else a guest-page-fault exception occurs. For example we are trying to access address 0xffff_ffff_ff01_0000 with only G-translation enabled. So expected behavior is to generate exception. But qemu doesn't generate such exception. For the old check, we get va_bits == 41, mask == (1 << 24) - 1, masked_msbs == (0xffff_ffff_ff01_0000 >> 40) & mask == mask. Accordingly, the condition masked_msbs != 0 && masked_msbs != mask is not fulfilled and the check passes. Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230418075423.26217-1-irina.ryapolova@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng
When reading a non-existent CSR QEMU should raise illegal instruction exception, but currently it just exits due to the g_assert() check. This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617. Some comments are also added to indicate that predicate() must be provided for an implemented CSR. Reported-by: Fei Wu <fei2.wu@intel.com> Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza
This new abstract type will be used to differentiate between static and non-static CPUs in query-cpu-definitions. All generic CPUs were changed to be of this type. Named CPUs are kept as TYPE_RISCV_CPU and will still be considered static. This is the output of query-cpu-definitions after this change for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": true, "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": true, "deprecated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": true, "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": true, "deprecated": false} ]} Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230411183511.189632-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add query-cpy-definitions supportDaniel Henrique Barboza
This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target: $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}] } Next patch will introduce a way to tell whether a given CPU is static or not. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza
QMP CPU commands are usually implemented by a separated file, <arch>-qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch, but first we need a cpu-qom.h header with the definitions of TYPE_RISCV_CPU and RISCVCPUClass declarations. These were moved from cpu.h to the new file, and cpu.h now includes "cpu-qom.h". Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230411183511.189632-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson
Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-26-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-26-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson
We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-25-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-25-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-24-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-24-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson
If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-23-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-23-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Suppress pte update with is_debugRichard Henderson
The debugger should not modify PTE_A or PTE_D. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-22-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-22-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Move leaf pte processing out of level loopRichard Henderson
Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-21-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-21-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Hoist pbmte and hade out of the level loopRichard Henderson
These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-20-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-20-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson
Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-19-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-19-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual. However, it matches the behavior for MPV. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-18-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-18-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-17-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-17-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson
The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-16-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-16-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-15-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-15-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson
Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-14-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-14-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson
In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-13-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-13-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson
We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-11-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-11-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Use cpu_ld*_code_mmu for HLVXRichard Henderson
Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-10-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-10-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window is usually opened up for a very limited time through MSTATUS.SUM, the overhead is too much if tlb_flush() gets called for every SUM change. This patch creates a separate MMU index for S+SUM, so that it's not necessary to flush tlb anymore when SUM changes. This is similar to how ARM handles Privileged Access Never (PAN). Result of 'pipe 10' from unixbench boosts from 223656 to 1705006. Many other syscalls benefit a lot from this too. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fei Wu <fei2.wu@intel.com> Message-Id: <20230324054154.414846-3-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-8-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-8-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Here an individual priv field is added into TB_FLAGS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Fei Wu <fei2.wu@intel.com> Message-Id: <20230324054154.414846-2-fei2.wu@intel.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-7-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-7-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
Once we mistook the vstart directly from the env->vstart. As env->vstart is not a constant, we should record it in the tb flags if we want to use it in translation. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230324143031.1093-5-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-6-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-6-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-5-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-5-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230324143031.1093-4-zhiwei_liu@linux.alibaba.com> [rth: Adjust trans_rvf.c.inc as well; use the typedef] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-4-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-4-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
The pointer masking is the only extension that directly use status. The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230324143031.1093-3-zhiwei_liu@linux.alibaba.com> [rth: Add a typedef for the enum] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-3-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-3-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
Virt enabled state is not a constant, so we should put it into tb flags. Thus we can use it like a constant condition at translation phase. Reported-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230324143031.1093-2-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230325105429.1142530-2-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: fix H extension TVM trapYi Chen
- Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled. - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled. - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes SFENCE.VMA/SINVAL.VMA or VS-mode executes SFENCE.VMA/SINVAL.VMA with HSTATUS.VTVM enabled. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes HFENCE.GVMA/HFENCE.VVMA/HINVAL.GVMA/HINVAL.VVMA. Signed-off-by: Yi Chen <chenyi2000@zju.edu.cn> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406101559.39632-1-chenyi2000@zju.edu.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li
Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done by check currently. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230408135908.25269-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 21:32:01 +0000