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AgeCommit message (Expand)Author
2023-06-13target/riscv: Update pmp_get_tlb_size()Weiwei Li
2023-06-13target/riscv: rework write_misa()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: validate extensions before riscv_timer_init()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add priv_spec validate/disable_exts helpersDaniel Henrique Barboza
2023-06-13target/riscv: Update check for Zca/Zcf/ZcdWeiwei Li
2023-06-13target/riscv: Mask the implicitly enabled extensions in isa_string based on p...Weiwei Li
2023-06-13target/riscv: add PRIV_VERSION_LATESTDaniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove set_priv_version()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: remove set_vext_version()Daniel Henrique Barboza
2023-06-13target/riscv/cpu.c: add riscv_cpu_validate_v()Daniel Henrique Barboza
2023-06-13target/riscv: Move zc* out of the experimental propertiesWeiwei Li
2023-06-13target/riscv/vector_helper.c: skip set tail when vta is zeroDaniel Henrique Barboza
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson
2023-06-05tcg: Split out tcg/oversized-guest.hRichard Henderson
2023-05-05target/riscv: add Ventana's Veyron V1 CPURahul Pathak
2023-05-05riscv: Make sure an exception is raised if a pte is malformedAlexandre Ghiti
2023-05-05target/riscv: Fix Guest Physical Address TranslationIrina Ryapolova
2023-05-05target/riscv: Restore the predicate() NULL check behaviorBin Meng
2023-05-05target/riscv: add TYPE_RISCV_DYNAMIC_CPUDaniel Henrique Barboza
2023-05-05target/riscv: add query-cpy-definitions supportDaniel Henrique Barboza
2023-05-05target/riscv: add CPU QOM headerDaniel Henrique Barboza
2023-05-05target/riscv: Reorg sum check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Reorg access check in get_physical_addressRichard Henderson
2023-05-05target/riscv: Merge checks for reserved pte flagsRichard Henderson
2023-05-05target/riscv: Don't modify SUM with is_debugRichard Henderson
2023-05-05target/riscv: Suppress pte update with is_debugRichard Henderson
2023-05-05target/riscv: Move leaf pte processing out of level loopRichard Henderson
2023-05-05target/riscv: Hoist pbmte and hade out of the level loopRichard Henderson
2023-05-05target/riscv: Hoist second stage mode change to callersRichard Henderson
2023-05-05target/riscv: Check SUM in the correct registerRichard Henderson
2023-05-05target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_indexRichard Henderson
2023-05-05target/riscv: Move hstatus.spvp check to check_access_hlsvRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_2stageRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_privRichard Henderson
2023-05-05target/riscv: Introduce mmuidx_sumRichard Henderson
2023-05-05target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BITRichard Henderson
2023-05-05target/riscv: Handle HLV, HSV via helpersRichard Henderson
2023-05-05target/riscv: Use cpu_ld*_code_mmu for HLVXRichard Henderson
2023-05-05target/riscv: Reduce overhead of MSTATUS_SUM changeFei Wu
2023-05-05target/riscv: Separate priv from mmu_idxFei Wu
2023-05-05target/riscv: Add a tb flags field for vstartLIU Zhiwei
2023-05-05target/riscv: Remove mstatus_hs_{fs, vs} from tb_flagsRichard Henderson
2023-05-05target/riscv: Encode the FS and VS on a normal way for tb flagsLIU Zhiwei
2023-05-05target/riscv: Add a general status enum for extensionsLIU Zhiwei
2023-05-05target/riscv: Extract virt enabled state from tb flagsLIU Zhiwei
2023-05-05target/riscv: fix H extension TVM trapYi Chen
2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li
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