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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2023-10-12
target/riscv: move riscv_tcg_ops to tcg-cpu.c
Daniel Henrique Barboza
2023-10-12
target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c
Daniel Henrique Barboza
2023-10-12
target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()
Daniel Henrique Barboza
2023-10-12
target/riscv: introduce TCG AccelCPUClass
Daniel Henrique Barboza
2023-10-12
target/riscv: Clear CSR values at reset and sync MPSTATE with host
liguang.zhang
2023-10-12
target/riscv/cpu.c: consider user option with RVG
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()
Daniel Henrique Barboza
2023-10-12
target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
Daniel Henrique Barboza
2023-10-12
target/riscv: make CPUCFG() macro public
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled
Daniel Henrique Barboza
2023-10-12
target/riscv: deprecate the 'any' CPU type
Daniel Henrique Barboza
2023-10-12
target/riscv: add 'max' CPU type
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: limit cfg->vext_spec log message
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]
Daniel Henrique Barboza
2023-10-12
target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: split kvm prop handling to its own helper
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: skip 'bool' check when filtering KVM props
Daniel Henrique Barboza
2023-10-12
target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
Daniel Henrique Barboza
2023-10-11
hw/core/cpu: Return static value with gdb_arch_name()
Akihiko Odaki
2023-10-07
meson: Rename target_softmmu_arch -> target_system_arch
Philippe Mathieu-Daudé
2023-10-07
tcg: Correct invalid mentions of 'softmmu' by 'system-mode'
Philippe Mathieu-Daudé
2023-10-04
accel/tcg: Remove cpu_set_cpustate_pointers
Richard Henderson
2023-10-04
accel/tcg: Replace CPUState.env_ptr with cpu_env()
Richard Henderson
2023-10-03
tcg: Rename cpu_env to tcg_env
Richard Henderson
2023-10-03
accel/tcg: Move CPUNegativeOffsetState into CPUState
Richard Henderson
2023-10-03
target/*: Add instance_align to all cpu base classes
Richard Henderson
2023-09-29
target/riscv: vector_helper: Fixup local variables shadowing
Alistair Francis
2023-09-29
target/riscv: cpu: Fixup local variables shadowing
Alistair Francis
2023-09-11
target/riscv: don't read CSR in riscv_csrrw_do64
Nikita Shubin
2023-09-11
target/riscv: Align the AIA model to v1.0 ratified spec
Tommy Wu
2023-09-11
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
Leon Schuermann
2023-09-11
target/riscv: Allocate itrigger timers only once
Akihiko Odaki
2023-09-11
target/riscv: Use accelerated helper for AES64KS1I
Ard Biesheuvel
2023-09-11
hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
Daniel Henrique Barboza
2023-09-11
riscv: zicond: make non-experimental
Vineet Gupta
2023-09-11
target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0
Daniel Henrique Barboza
2023-09-11
target/riscv: Update CSR bits name for svadu extension
Weiwei Li
2023-09-11
target/riscv: Create an KVM AIA irqchip
Yong-Xuan Wang
2023-09-11
target/riscv: check the in-kernel irqchip support
Yong-Xuan Wang
2023-09-11
target/riscv: Fix zfa fleq.d and fltq.d
LIU Zhiwei
2023-09-11
target/riscv: Add Zihintntl extension ISA string to DTS
Jason Chien
2023-09-11
target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren
Rob Bradford
2023-09-11
target/riscv: Add Zvksed ISA extension support
Max Chou
2023-09-11
target/riscv: Add Zvkg ISA extension support
Nazar Kazakov
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