| Age | Commit message (Expand) | Author |
|---|
| 2023-05-05 | target/riscv: add Ventana's Veyron V1 CPU | Rahul Pathak |
| 2023-05-05 | riscv: Make sure an exception is raised if a pte is malformed | Alexandre Ghiti |
| 2023-05-05 | target/riscv: Fix Guest Physical Address Translation | Irina Ryapolova |
| 2023-05-05 | target/riscv: Restore the predicate() NULL check behavior | Bin Meng |
| 2023-05-05 | target/riscv: add TYPE_RISCV_DYNAMIC_CPU | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: add query-cpy-definitions support | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: add CPU QOM header | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: Reorg sum check in get_physical_address | Richard Henderson |
| 2023-05-05 | target/riscv: Reorg access check in get_physical_address | Richard Henderson |
| 2023-05-05 | target/riscv: Merge checks for reserved pte flags | Richard Henderson |
| 2023-05-05 | target/riscv: Don't modify SUM with is_debug | Richard Henderson |
| 2023-05-05 | target/riscv: Suppress pte update with is_debug | Richard Henderson |
| 2023-05-05 | target/riscv: Move leaf pte processing out of level loop | Richard Henderson |
| 2023-05-05 | target/riscv: Hoist pbmte and hade out of the level loop | Richard Henderson |
| 2023-05-05 | target/riscv: Hoist second stage mode change to callers | Richard Henderson |
| 2023-05-05 | target/riscv: Check SUM in the correct register | Richard Henderson |
| 2023-05-05 | target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index | Richard Henderson |
| 2023-05-05 | target/riscv: Move hstatus.spvp check to check_access_hlsv | Richard Henderson |
| 2023-05-05 | target/riscv: Introduce mmuidx_2stage | Richard Henderson |
| 2023-05-05 | target/riscv: Introduce mmuidx_priv | Richard Henderson |
| 2023-05-05 | target/riscv: Introduce mmuidx_sum | Richard Henderson |
| 2023-05-05 | target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT | Richard Henderson |
| 2023-05-05 | target/riscv: Handle HLV, HSV via helpers | Richard Henderson |
| 2023-05-05 | target/riscv: Use cpu_ld*_code_mmu for HLVX | Richard Henderson |
| 2023-05-05 | target/riscv: Reduce overhead of MSTATUS_SUM change | Fei Wu |
| 2023-05-05 | target/riscv: Separate priv from mmu_idx | Fei Wu |
| 2023-05-05 | target/riscv: Add a tb flags field for vstart | LIU Zhiwei |
| 2023-05-05 | target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags | Richard Henderson |
| 2023-05-05 | target/riscv: Encode the FS and VS on a normal way for tb flags | LIU Zhiwei |
| 2023-05-05 | target/riscv: Add a general status enum for extensions | LIU Zhiwei |
| 2023-05-05 | target/riscv: Extract virt enabled state from tb flags | LIU Zhiwei |
| 2023-05-05 | target/riscv: fix H extension TVM trap | Yi Chen |
| 2023-05-05 | target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx | Weiwei Li |
| 2023-05-05 | target/riscv: Legalize MPP value in write_mstatus | Weiwei Li |
| 2023-05-05 | target/riscv: Use PRV_RESERVED instead of PRV_H | Weiwei Li |
| 2023-05-05 | target/riscv: Fix the mstatus.MPP value after executing MRET | Weiwei Li |
| 2023-05-05 | target/riscv/cpu.c: redesign register_cpu_props() | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: add RVG and remove cpu->cfg.ext_g | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove riscv_cpu_sync_misa_cfg() | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_v | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_j | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_h | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_u | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_s | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_m | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_e | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_i | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_f | Daniel Henrique Barboza |
| 2023-05-05 | target/riscv: remove cpu->cfg.ext_d | Daniel Henrique Barboza |
