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AgeCommit message (Expand)Author
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li
2022-03-03target/riscv: add support for zdinxWeiwei Li
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel
2022-02-16target/riscv: Add AIA cpu featureAnup Patel
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei
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