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AgeCommit message (Expand)Author
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker
2023-01-20target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng
2023-01-20target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei
2023-01-04target/riscv: Use QEMU_IOTHREAD_LOCK_GUARD in riscv_cpu_update_mipRichard Henderson
2022-12-16target/riscv: Convert to 3-phase resetPeter Maydell
2022-12-14cleanup: Tweak and re-run return_directly.cocciMarkus Armbruster
2022-10-26Merge tag 'pull-tcg-20221026' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
2022-10-26target/riscv: Convert to tcg_ops restore_state_to_opcRichard Henderson
2022-10-24treewide: Remove the unnecessary space before semicolonBin Meng
2022-10-14target/riscv: pmp: Fixup TLB size calculationAlistair Francis
2022-10-13Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
2022-10-10kvm: allow target-specific accelerator propertiesPaolo Bonzini
2022-10-06dump: Replace opaque DumpState pointer with a typed oneJanosch Frank
2022-10-04accel/tcg: Introduce tb_pc and log_pcRichard Henderson
2022-10-04hw/core: Add CPUClass.get_pcRichard Henderson
2022-09-27target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unorderedYang Liu
2022-09-27target/riscv: rvv-1.0: Simplify vfwredsum codeYang Liu
2022-09-27target/riscv: debug: Add initial support of type 6 triggerFrank Chang
2022-09-27target/riscv: debug: Check VU/VS modes for type 2 triggerFrank Chang
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