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AgeCommit message (Expand)Author
2023-05-05target/riscv: Fix format for indentationWeiwei Li
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei
2023-05-05target/riscv: Add support for ZceWeiwei Li
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li
2023-05-05target/riscv: add support for Zca extensionWeiwei Li
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich
2023-05-05target/riscv: refactor Zicond supportPhilipp Tomsich
2023-05-05target/riscv: Simplify arguments for riscv_csrrw_checkWeiwei Li
2023-05-05target/riscv: Simplify type conversion for CPURISCVStateWeiwei Li
2023-05-05target/riscv: Simplify getting RISCVCPU pointer from envWeiwei Li
2023-05-05target/riscv: Fix priv version dependency for vector and zfhLIU Zhiwei
2023-05-05target/riscv: Avoid env_archcpu() when reading RISCVCPUConfigWeiwei Li
2023-03-13target/riscv: Remove `NB_MMU_MODES` defineAnton Johansson
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée
2023-03-07includes: move tb_flush into its own headerAlex Bennée
2023-03-07Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti
2023-03-06riscv: Pass Object to register_cpu_props instead of DeviceStateAlexandre Ghiti
2023-03-05target/riscv: cpu: Implement get_arch_id callbackMayuresh Chitale
2023-03-05target/riscv: Avoid tcg_const_*Richard Henderson
2023-03-05target/riscv: Drop tcg_temp_freeRichard Henderson
2023-03-05target/riscv: Drop temp_newRichard Henderson
2023-03-05target/riscv: Drop ftemp_newRichard Henderson
2023-03-05target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholderChristoph Muellner
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt...Peter Maydell
2023-03-01Merge patch series "target/riscv: some vector_helper.c cleanups"Palmer Dabbelt
2023-03-01target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfigDaniel Henrique Barboza
2023-03-01target/riscv/vector_helper.c: create vext_set_tail_elems_1s()Daniel Henrique Barboza
2023-03-01Merge patch series "RISCVCPUConfig related cleanups"Palmer Dabbelt
2023-03-01target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfigDaniel Henrique Barboza
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