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AgeCommit message (Expand)Author
2023-10-07meson: Rename target_softmmu_arch -> target_system_archPhilippe Mathieu-Daudé
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé
2023-10-04accel/tcg: Remove cpu_set_cpustate_pointersRichard Henderson
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson
2023-10-03target/*: Add instance_align to all cpu base classesRichard Henderson
2023-09-29target/riscv: vector_helper: Fixup local variables shadowingAlistair Francis
2023-09-29target/riscv: cpu: Fixup local variables shadowingAlistair Francis
2023-09-11target/riscv: don't read CSR in riscv_csrrw_do64Nikita Shubin
2023-09-11target/riscv: Align the AIA model to v1.0 ratified specTommy Wu
2023-09-11target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changesLeon Schuermann
2023-09-11target/riscv: Allocate itrigger timers only onceAkihiko Odaki
2023-09-11target/riscv: Use accelerated helper for AES64KS1IArd Biesheuvel
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza
2023-09-11riscv: zicond: make non-experimentalVineet Gupta
2023-09-11target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0Daniel Henrique Barboza
2023-09-11target/riscv: Update CSR bits name for svadu extensionWeiwei Li
2023-09-11target/riscv: Create an KVM AIA irqchipYong-Xuan Wang
2023-09-11target/riscv: check the in-kernel irqchip supportYong-Xuan Wang
2023-09-11target/riscv: Fix zfa fleq.d and fltq.dLIU Zhiwei
2023-09-11target/riscv: Add Zihintntl extension ISA string to DTSJason Chien
2023-09-11target/riscv: Implement WARL behaviour for mcountinhibit/mcounterenRob Bradford
2023-09-11target/riscv: Add Zvksed ISA extension supportMax Chou
2023-09-11target/riscv: Add Zvkg ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvksh ISA extension supportLawrence Hunter
2023-09-11target/riscv: Add Zvknh ISA extension supportKiran Ostrolenk
2023-09-11target/riscv: Add Zvkned ISA extension supportNazar Kazakov
2023-09-11target/riscv: Add Zvbb ISA extension supportDickon Hood
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk
2023-09-11target/riscv: Refactor translation of vector-widening instructionDickon Hood
2023-09-11target/riscv: Move vector translation checksNazar Kazakov
2023-09-11target/riscv: Add Zvbc ISA extension supportLawrence Hunter
2023-09-11target/riscv: Remove redundant "cpu_vl == 0" checksNazar Kazakov
2023-09-11target/riscv: Refactor vector-vector translation macroKiran Ostrolenk
2023-09-11target/riscv: Refactor some of the generic vector functionalityKiran Ostrolenk
2023-09-11target/riscv: Use existing lookup tables for MixColumnsArd Biesheuvel
2023-09-11target/riscv: Fix page_check_range use in fault-only-firstLIU Zhiwei
2023-09-11target/riscv/cpu.c: add smepmp isa stringDaniel Henrique Barboza
2023-09-11target/riscv/cpu.c: add zmmul isa stringDaniel Henrique Barboza
2023-09-11target/riscv/cpu.c: do not run 'host' CPU with TCGDaniel Henrique Barboza
2023-09-08riscv: spelling fixesMichael Tokarev
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé
2023-08-31target/helpers: Remove unnecessary 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
2023-08-31target/riscv/pmu: Restrict 'qemu/log.h' include to sourcePhilippe Mathieu-Daudé
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson
2023-08-22kvm: Introduce kvm_arch_get_default_type hookAkihiko Odaki
2023-08-11target/riscv/kvm.c: fix mvendorid size in vcpu_set_machine_ids()Daniel Henrique Barboza
2023-07-19target/riscv: Fix LMUL check to use VLENRob Bradford
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