slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-10-14	target/riscv: pmp: Fixup TLB size calculation	Alistair Francis
2022-10-13	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi
2022-10-10	kvm: allow target-specific accelerator properties	Paolo Bonzini
2022-10-06	dump: Replace opaque DumpState pointer with a typed one	Janosch Frank
2022-10-04	accel/tcg: Introduce tb_pc and log_pc	Richard Henderson
2022-10-04	hw/core: Add CPUClass.get_pc	Richard Henderson
2022-09-27	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	Yang Liu
2022-09-27	target/riscv: rvv-1.0: Simplify vfwredsum code	Yang Liu
2022-09-27	target/riscv: debug: Add initial support of type 6 trigger	Frank Chang
2022-09-27	target/riscv: debug: Check VU/VS modes for type 2 trigger	Frank Chang
2022-09-27	target/riscv: debug: Create common trigger actions function	Frank Chang
2022-09-27	target/riscv: debug: Introduce tinfo CSR	Frank Chang
2022-09-27	target/riscv: debug: Restrict the range of tselect value can be written	Frank Chang
2022-09-27	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	Frank Chang
2022-09-27	target/riscv: debug: Introduce build_tdata1() to build tdata1 register content	Frank Chang
2022-09-27	target/riscv: debug: Determine the trigger type from tdata1.type	Frank Chang
2022-09-27	target/riscv: Check the correct exception cause in vector GDB stub	Frank Chang
2022-09-27	target/riscv: Set the CPU resetvec directly	Alistair Francis
2022-09-27	target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml	Andrew Burgess
2022-09-27	target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}	Weiwei Li
2022-09-27	target/riscv: Remove sideleg and sedeleg	Rahul Pathak
2022-09-13	target/riscv: Honour -semihosting-config userspace=on and enable=on	Peter Maydell
2022-09-07	target/riscv: Update the privilege field for sscofpmf CSRs	Atish Patra
2022-09-07	hw/riscv: virt: Add PMU DT node to the device tree	Atish Patra
2022-09-07	target/riscv: Add few cache related PMU events	Atish Patra
2022-09-07	target/riscv: Simplify counter predicate function	Atish Patra
2022-09-07	target/riscv: Add sscofpmf extension support	Atish Patra
2022-09-07	target/riscv: Add vstimecmp support	Atish Patra
2022-09-07	target/riscv: Add stimecmp support	Atish Patra
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra
2022-09-07	target/riscv: Use official extension names for AIA CSRs	Anup Patel
2022-09-07	target/riscv: Add xicondops in ISA entry	Rahul Pathak
2022-09-07	target/riscv: Remove additional priv version check for mcountinhibit	Atish Patra
2022-09-07	target/riscv: Fix priority of csr related check in riscv_csrrw_check	Weiwei Li
2022-09-07	target/riscv: Add Zihintpause support	Dao Lu
2022-09-07	target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...	eopXD
2022-09-07	target/riscv: rvv: Add mask agnostic for vector permutation instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector mask instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector floating-point instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer comparison instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector integer shift instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vx instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vector load / store instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: rvv: Add mask agnostic for vv instructions	Yueh-Ting (eop) Chen
2022-09-07	target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V	Alexey Baturo
2022-09-07	target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...	Weiwei Li
2022-09-07	target/riscv: Fix checks in hmode/hmode32	Weiwei Li
2022-09-07	target/riscv: Add check for csrs existed with U extension	Weiwei Li
2022-09-07	target/riscv: Fix checkpatch warning may triggered in csr_ops table	Weiwei Li