| Age | Commit message (Expand) | Author |
|---|
| 2021-12-20 | target/riscv: zfh: half-precision computational | Kito Cheng |
| 2021-12-20 | target/riscv: zfh: half-precision load and store | Kito Cheng |
| 2021-11-17 | target/riscv: machine: Sort the .subsections | Bin Meng |
| 2021-11-02 | target/riscv: Make riscv_cpu_tlb_fill sysemu only | Richard Henderson |
| 2021-10-29 | target/riscv: change the api for RVF/RVD fmin/fmax | Chih-Min Chao |
| 2021-10-29 | target/riscv: remove force HS exception | Jose Martins |
| 2021-10-29 | target/riscv: fix VS interrupts forwarding to HS | Jose Martins |
| 2021-10-28 | target/riscv: Allow experimental J-ext to be turned on | Alexey Baturo |
| 2021-10-28 | target/riscv: Implement address masking functions required for RISC-V Pointer... | Anatoly Parshintsev |
| 2021-10-28 | target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr... | Alexey Baturo |
| 2021-10-28 | target/riscv: Print new PM CSRs in QEMU logs | Alexey Baturo |
| 2021-10-28 | target/riscv: Add J extension state description | Alexey Baturo |
| 2021-10-28 | target/riscv: Support CSRs required for RISC-V PM extension except for the h-... | Alexey Baturo |
| 2021-10-28 | target/riscv: Add CSR defines for RISC-V PM extension | Alexey Baturo |
| 2021-10-28 | target/riscv: Add J-extension into RISC-V | Alexey Baturo |
| 2021-10-22 | target/riscv: Compute mstatus.sd on demand | Richard Henderson |
| 2021-10-22 | target/riscv: Use riscv_csrrw_debug for cpu_dump | Richard Henderson |
| 2021-10-22 | target/riscv: Use gen_shift*_per_ol for RVB, RVI | Richard Henderson |
| 2021-10-22 | target/riscv: Use gen_unary_per_ol for RVB | Richard Henderson |
| 2021-10-22 | target/riscv: Adjust trans_rev8_32 for riscv64 | Richard Henderson |
| 2021-10-22 | target/riscv: Use gen_arith_per_ol for RVM | Richard Henderson |
| 2021-10-22 | target/riscv: Replace DisasContext.w with DisasContext.ol | Richard Henderson |
| 2021-10-22 | target/riscv: Replace is_32bit with get_xl/get_xlen | Richard Henderson |
| 2021-10-22 | target/riscv: Properly check SEW in amo_op | Richard Henderson |
| 2021-10-22 | target/riscv: Use REQUIRE_64BIT in amo_check64 | Richard Henderson |
| 2021-10-22 | target/riscv: Add MXL/SXL/UXL to TB_FLAGS | Richard Henderson |
| 2021-10-22 | target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl | Richard Henderson |
| 2021-10-22 | target/riscv: Split misa.mxl and misa.ext | Richard Henderson |
| 2021-10-22 | target/riscv: Create RISCVMXL enumeration | Richard Henderson |
| 2021-10-22 | target/riscv: Move cpu_get_tb_cpu_state out of line | Richard Henderson |
| 2021-10-22 | target/riscv: Organise the CPU properties | Alistair Francis |
| 2021-10-22 | target/riscv: Remove some unused macros | Alistair Francis |
| 2021-10-22 | target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh | Frank Chang |
| 2021-10-22 | target/riscv: Fix orc.b implementation | Philipp Tomsich |
| 2021-10-22 | target/riscv: line up all of the registers in the info register dump | Travis Geiselbrecht |
| 2021-10-22 | target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v | Frank Chang |
| 2021-10-15 | target/riscv: Remove exit_tb and lookup_and_goto_ptr | Richard Henderson |
| 2021-10-15 | target/riscv: Remove dead code after exception | Richard Henderson |
| 2021-10-07 | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() | Frank Chang |
| 2021-10-07 | target/riscv: Remove RVB (replaced by Zb[abcs]) | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add rev8 instruction, removing grev/grevi | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add a REQUIRE_32BIT macro | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbb-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add instructions of the Zbc-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbs-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) | Philipp Tomsich |
| 2021-10-07 | target/riscv: Remove the W-form instructions from Zbs | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zba-extension | Philipp Tomsich |
