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AgeCommit message (Expand)Author
2023-03-01target/riscv: Add support for Zvfh/zvfhmin extensionsWeiwei Li
2023-03-01target/riscv: Remove redundunt check for zve32f and zve64fWeiwei Li
2023-03-01target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.incWeiwei Li
2023-03-01target/riscv: Simplify check for Zve32f and Zve64fWeiwei Li
2023-03-01target/riscv: Indent fixes in cpu.cWeiwei Li
2023-03-01target/riscv: Add property check for Zvfh{min} extensionsWeiwei Li
2023-03-01target/riscv: Fix relationship between V, Zve*, F and DWeiwei Li
2023-03-01target/riscv: Add cfg properties for Zv* extensionsWeiwei Li
2023-03-01target/riscv: Simplify the check for Zfhmin and ZhinxminWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zhinxmin and ZhinxWeiwei Li
2023-03-01target/riscv: Fix the relationship between Zfhmin and ZfhWeiwei Li
2023-03-01target/riscv/cpu: remove CPUArchState::features and friendsDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_MMUDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_EPMPDaniel Henrique Barboza
2023-03-01target/riscv/cpu.c: error out if EPMP is enabled without PMPDaniel Henrique Barboza
2023-03-01target/riscv: remove RISCV_FEATURE_DEBUGDaniel Henrique Barboza
2023-03-01target/riscv: allow MISA writes as experimentalDaniel Henrique Barboza
2023-03-01target/riscv: do not mask unsupported QEMU extensions in write_misa()Daniel Henrique Barboza
2023-03-01target/riscv: introduce riscv_cpu_cfg()Daniel Henrique Barboza
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson
2023-03-01target/riscv: Replace `tb_pc()` with `tb->pc`Anton Johansson
2023-02-27target/riscv/cpu: Move Floating-Point fields closerPhilippe Mathieu-Daudé
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza
2023-02-23target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
2023-02-08riscv: Clean up includesMarkus Armbruster
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
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