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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2023-05-05
target/riscv: remove cpu->cfg.ext_s
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_m
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_e
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_i
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_f
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_d
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_c
Daniel Henrique Barboza
2023-05-05
target/riscv: remove cpu->cfg.ext_a
Daniel Henrique Barboza
2023-05-05
target/riscv: introduce riscv_cpu_add_misa_properties()
Daniel Henrique Barboza
2023-05-05
target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data
Daniel Henrique Barboza
2023-05-05
target/riscv: remove MISA properties from isa_edata_arr[]
Daniel Henrique Barboza
2023-05-05
target/riscv: sync env->misa_ext* with cpu->cfg in realize()
Daniel Henrique Barboza
2023-05-05
target/riscv: Fix lines with over 80 characters
Weiwei Li
2023-05-05
target/riscv: Fix format for comments
Weiwei Li
2023-05-05
target/riscv: Fix format for indentation
Weiwei Li
2023-05-05
target/riscv: Remove riscv_cpu_virt_enabled()
Weiwei Li
2023-05-05
target/riscv: Set opcode to env->bins for illegal/virtual instruction fault
Weiwei Li
2023-05-05
target/riscv: Fix addr type for get_physical_address
Weiwei Li
2023-05-05
target/riscv: Remove redundant parentheses
Weiwei Li
2023-05-05
target/riscv: Convert env->virt to a bool env->virt_enabled
LIU Zhiwei
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Remove check on RVH for riscv_cpu_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Remove redundant check on RVH
Weiwei Li
2023-05-05
target/riscv: Remove redundant call to riscv_cpu_virt_enabled
Weiwei Li
2023-05-05
target/riscv: Fix itrigger when icount is used
LIU Zhiwei
2023-05-05
target/riscv: Add support for Zce
Weiwei Li
2023-05-05
target/riscv: expose properties for Zc* extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcmt extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcmp extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcb extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcd extension
Weiwei Li
2023-05-05
target/riscv: add support for Zcf extension
Weiwei Li
2023-05-05
target/riscv: add support for Zca extension
Weiwei Li
2023-05-05
target/riscv: add cfg properties for Zc* extension
Weiwei Li
2023-05-05
target/riscv: fix invalid riscv,event-to-mhpmcounters entry
Conor Dooley
2023-05-05
target/riscv: redirect XVentanaCondOps to use the Zicond functions
Philipp Tomsich
2023-05-05
target/riscv: refactor Zicond support
Philipp Tomsich
2023-05-05
target/riscv: Simplify arguments for riscv_csrrw_check
Weiwei Li
2023-05-05
target/riscv: Simplify type conversion for CPURISCVState
Weiwei Li
2023-05-05
target/riscv: Simplify getting RISCVCPU pointer from env
Weiwei Li
2023-05-05
target/riscv: Fix priv version dependency for vector and zfh
LIU Zhiwei
2023-05-05
target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Weiwei Li
2023-03-13
target/riscv: Remove `NB_MMU_MODES` define
Anton Johansson
2023-03-07
gdbstub: move register helpers into standalone include
Alex Bennée
2023-03-07
includes: move tb_flush into its own header
Alex Bennée
2023-03-07
Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt...
Peter Maydell
2023-03-06
riscv: Introduce satp mode hw capabilities
Alexandre Ghiti
2023-03-06
riscv: Allow user to set the satp mode
Alexandre Ghiti
2023-03-06
riscv: Change type of valid_vm_1_10_[32|64] to bool
Alexandre Ghiti
2023-03-06
riscv: Pass Object to register_cpu_props instead of DeviceState
Alexandre Ghiti
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