slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-04-22	target/riscv: cpu: Enable native debug feature	Bin Meng
2022-04-22	target/riscv: machine: Add debug state description	Bin Meng
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng
2022-04-22	target/riscv: cpu: Add a config option for native debug	Bin Meng
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng
2022-04-22	hw/intc: Make RISC-V ACLINT mtime MMIO register writable	Frank Chang
2022-04-22	target/riscv/pmp: fix NAPOT range computation overflow	Nicolas Pitre
2022-04-22	target/riscv: Use cpu_loop_exit_restore directly from mmu faults	Richard Henderson
2022-04-22	target/riscv: fix start byte for vmv<nf>r.v when vstart != 0	Weiwei Li
2022-04-22	target/riscv: Add isa extenstion strings to the device tree	Atish Patra
2022-04-22	target/riscv: misa to ISA string conversion fix	Tsukasa OI
2022-04-22	target/riscv: optimize helper for vmv<nr>r.v	Weiwei Li
2022-04-22	target/riscv: optimize condition assign for scale < 0	Weiwei Li
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng
2022-04-22	target/riscv: Allow software access to MIP SEIP	Alistair Francis
2022-04-22	target/riscv: cpu: Fixup indentation	Alistair Francis
2022-04-22	target/riscv: Enable privileged spec version 1.12	Atish Patra
2022-04-22	target/riscv: Add envcfg CSRs support	Atish Patra
2022-04-22	target/riscv: Add support for mconfigptr	Atish Patra
2022-04-22	target/riscv: Introduce privilege version field in the CSR ops.	Atish Patra
2022-04-22	target/riscv: Add the privileged spec version 1.12.0	Atish Patra
2022-04-22	target/riscv: Define simpler privileged spec version numbering	Atish Patra
2022-04-21	compiler.h: replace QEMU_NORETURN with G_NORETURN	Marc-André Lureau
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson
2022-04-06	Remove qemu-common.h include from most units	Marc-André Lureau
2022-04-06	Move CPU softfloat unions to cpu-float.h	Marc-André Lureau
2022-04-06	Replace config-time define HOST_WORDS_BIGENDIAN	Marc-André Lureau
2022-04-01	target/riscv: rvv: Add missing early exit condition for whole register load/s...	Yueh-Ting (eop) Chen
2022-04-01	target/riscv: Avoid leaking "no translation" TLB entries	Palmer Dabbelt
2022-03-06	target: Use ArchCPU as interface to target CPU	Philippe Mathieu-Daudé
2022-03-06	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	Philippe Mathieu-Daudé
2022-03-06	target: Use CPUArchState as interface to target-specific CPU state	Philippe Mathieu-Daudé
2022-03-06	target: Include missing 'cpu.h'	Philippe Mathieu-Daudé
2022-03-06	misc: Add missing "sysemu/cpu-timers.h" include	Philippe Mathieu-Daudé
2022-03-03	target/riscv: expose zfinx, zdinx, zhinx{min} properties	Weiwei Li
2022-03-03	target/riscv: add support for zhinx/zhinxmin	Weiwei Li
2022-03-03	target/riscv: add support for zdinx	Weiwei Li
2022-03-03	target/riscv: add support for zfinx	Weiwei Li
2022-03-03	target/riscv: hardwire mstatus.FS to zero when enable zfinx	Weiwei Li
2022-03-03	target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}	Weiwei Li
2022-03-03	target/riscv: fix inverted checks for ext_zb[abcs]	Philipp Tomsich
2022-02-21	target: Add missing "qemu/timer.h" include	Philippe Mathieu-Daudé
2022-02-16	target/riscv: add support for svpbmt extension	Weiwei Li
2022-02-16	target/riscv: add support for svinval extension	Weiwei Li
2022-02-16	target/riscv: add support for svnapot extension	Weiwei Li
2022-02-16	target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE	Weiwei Li
2022-02-16	target/riscv: Ignore reserved bits in PTE for RV64	Guo Ren
2022-02-16	target/riscv: Allow users to force enable AIA CSRs in HART	Anup Patel
2022-02-16	target/riscv: Implement AIA IMSIC interface CSRs	Anup Patel
2022-02-16	target/riscv: Implement AIA xiselect and xireg CSRs	Anup Patel