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AgeCommit message (Expand)Author
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé
2023-02-23target/riscv: Fix vslide1up.vf and vslide1down.vfLIU Zhiwei
2023-02-23target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()Daniel Henrique Barboza
2023-02-23target/riscv: Smepmp: Skip applying default rules when address matchesHimanshu Chauhan
2023-02-23target/riscv: Remove privileged spec version restriction for RVVFrank Chang
2023-02-08riscv: Clean up includesMarkus Armbruster
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-01-20target/riscv: Remove helper_set_rod_rounding_modeRichard Henderson
2023-01-20target/riscv: Introduce helper_set_rounding_mode_chkfrmRichard Henderson
2023-01-20target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1Andrew Bresticker
2023-01-20target/riscv: Fix up masking of vsip/vsie accessesAndrew Bresticker
2023-01-20target/riscv: Use TARGET_FMT_lx for env->mhartidBin Meng
2023-01-20target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()Daniel Henrique Barboza
2023-01-20target/riscv/cpu: set cpu->cfg in register_cpu_props()Daniel Henrique Barboza
2023-01-20target/riscv/cpu.c: Fix elen checkDongxue Zhang
2023-01-20hw/char: riscv_htif: Move registers from CPUArchState to HTIFStateBin Meng
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
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