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AgeCommit message (Expand)Author
2020-07-02target/riscv: vector integer comparison instructionsLIU Zhiwei
2020-07-02target/riscv: vector narrowing integer right shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector single-width bit shift instructionsLIU Zhiwei
2020-07-02target/riscv: vector bitwise logical instructionsLIU Zhiwei
2020-07-02target/riscv: vector integer add-with-carry / subtract-with-borrow instructionsLIU Zhiwei
2020-07-02target/riscv: vector widening integer add and subtractLIU Zhiwei
2020-07-02target/riscv: vector single-width integer add and subtractLIU Zhiwei
2020-07-02target/riscv: add vector amo operationsLIU Zhiwei
2020-07-02target/riscv: add fault-only-first unit stride loadLIU Zhiwei
2020-07-02target/riscv: add vector index load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add vector stride load and store instructionsLIU Zhiwei
2020-07-02target/riscv: add an internals.h headerLIU Zhiwei
2020-07-02target/riscv: add vector configure instructionLIU Zhiwei
2020-07-02target/riscv: support vector extension csrLIU Zhiwei
2020-07-02target/riscv: implementation-defined constant parametersLIU Zhiwei
2020-07-02target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang
2020-06-08Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell
2020-06-05target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis
2020-04-29target/riscv: Add a sifive-e34 cpu typeCorey Wharton
2020-04-29riscv: Fix Stage2 SV32 page table walkAnup Patel
2020-04-29riscv: AND stage-1 and stage-2 protection flagsAlistair Francis
2020-04-29riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée
2020-03-16target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal
2020-03-16target/riscv: Correctly implement TSR trapAlistair Francis
2020-03-05RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis
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