slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2022-05-24	target/riscv: add zicsr/zifencei to isa_string	Hongren (Zenithal) Zheng
2022-05-24	target/riscv: Set [m\|s]tval for both illegal and virtual instruction traps	Anup Patel
2022-05-24	target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode	Anup Patel
2022-05-24	target/riscv: Fix csr number based privilege checking	Anup Patel
2022-05-24	target/riscv: Fix typo of mimpid cpu option	Frank Chang
2022-05-24	target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize	Weiwei Li
2022-05-24	target/riscv: Move/refactor ISA extension checks	Tsukasa OI
2022-05-24	target/riscv: FP extension requirements	Tsukasa OI
2022-05-24	target/riscv: Change "G" expansion	Tsukasa OI
2022-05-24	target/riscv: Disable "G" by default	Tsukasa OI
2022-05-24	target/riscv: Fix coding style on "G" expansion	Tsukasa OI
2022-05-24	target/riscv: Add short-isa-string option	Tsukasa OI
2022-05-24	target/riscv: Move Zhinx* extensions on ISA string	Tsukasa OI
2022-05-24	target/riscv: rvv: Fix early exit condition for whole register load/store	eopXD
2022-05-24	target/riscv: Fix VS mode hypervisor CSR access	Dylan Reid
2022-05-11	Normalize header guard symbol definition	Markus Armbruster
2022-05-11	Clean up ill-advised or unusual header guards	Markus Armbruster
2022-04-29	target/riscv: add scalar crypto related extenstion strings to isa_string	Weiwei Li
2022-04-29	target/riscv: Fix incorrect PTE merge in walk_pte	Ralf Ramsauer
2022-04-29	target/riscv: rvk: expose zbk* and zk* properties	Weiwei Li
2022-04-29	target/riscv: rvk: add CSR support for Zkr	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zksed/zksh extension	Weiwei Li
2022-04-29	target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...	Weiwei Li
2022-04-29	target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...	Weiwei Li
2022-04-29	target/riscv: rvk: add support for sha256 related instructions in zknh extension	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zkne/zknd extension in RV64	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zknd/zkne extension in RV32	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zbkx extension	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zbkc extension	Weiwei Li
2022-04-29	target/riscv: rvk: add support for zbkb extension	Weiwei Li
2022-04-29	target/riscv: rvk: add cfg properties for zbk* and zk*	Weiwei Li
2022-04-29	target/riscv: Support configuarable marchid, mvendorid, mipid CSR values	Frank Chang
2022-04-22	target/riscv: cpu: Enable native debug feature	Bin Meng
2022-04-22	target/riscv: machine: Add debug state description	Bin Meng
2022-04-22	target/riscv: csr: Hook debug CSR read/write	Bin Meng
2022-04-22	target/riscv: cpu: Add a config option for native debug	Bin Meng
2022-04-22	target/riscv: debug: Implement debug related TCGCPUOps	Bin Meng
2022-04-22	hw/intc: Make RISC-V ACLINT mtime MMIO register writable	Frank Chang
2022-04-22	target/riscv/pmp: fix NAPOT range computation overflow	Nicolas Pitre
2022-04-22	target/riscv: Use cpu_loop_exit_restore directly from mmu faults	Richard Henderson
2022-04-22	target/riscv: fix start byte for vmv<nf>r.v when vstart != 0	Weiwei Li
2022-04-22	target/riscv: Add isa extenstion strings to the device tree	Atish Patra
2022-04-22	target/riscv: misa to ISA string conversion fix	Tsukasa OI
2022-04-22	target/riscv: optimize helper for vmv<nr>r.v	Weiwei Li
2022-04-22	target/riscv: optimize condition assign for scale < 0	Weiwei Li
2022-04-22	target/riscv: Add initial support for the Sdtrig extension	Bin Meng
2022-04-22	target/riscv: Allow software access to MIP SEIP	Alistair Francis
2022-04-22	target/riscv: cpu: Fixup indentation	Alistair Francis
2022-04-22	target/riscv: Enable privileged spec version 1.12	Atish Patra
2022-04-22	target/riscv: Add envcfg CSRs support	Atish Patra