| Age | Commit message (Expand) | Author |
|---|
| 2020-04-29 | target/riscv: Add a sifive-e34 cpu type | Corey Wharton |
| 2020-04-29 | riscv: Fix Stage2 SV32 page table walk | Anup Patel |
| 2020-04-29 | riscv: AND stage-1 and stage-2 protection flags | Alistair Francis |
| 2020-04-29 | riscv: Don't use stage-2 PTE lookup protection flags | Alistair Francis |
| 2020-03-19 | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ... | Peter Maydell |
| 2020-03-17 | cpu: Use DeviceClass reset instead of a special CPUClass reset | Peter Maydell |
| 2020-03-17 | gdbstub: extend GByteArray to read register helpers | Alex Bennée |
| 2020-03-16 | target/riscv: Fix VS mode interrupts forwarding. | Rajnesh Kanwal |
| 2020-03-16 | target/riscv: Correctly implement TSR trap | Alistair Francis |
| 2020-03-05 | RISC-V: Add a missing "," in riscv_excp_names | Palmer Dabbelt |
| 2020-02-27 | target/riscv: Emulate TIME CSRs for privileged mode | Anup Patel |
| 2020-02-27 | target/riscv: Allow enabling the Hypervisor extension | Alistair Francis |
| 2020-02-27 | target/riscv: Add the MSTATUS_MPV_ISSET helper macro | Alistair Francis |
| 2020-02-27 | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis |
| 2020-02-27 | target/riscv: Set htval and mtval2 on execptions | Alistair Francis |
| 2020-02-27 | target/riscv: Raise the new execptions when 2nd stage translation fails | Alistair Francis |
| 2020-02-27 | target/riscv: Implement second stage MMU | Alistair Francis |
| 2020-02-27 | target/riscv: Allow specifying MMU stage | Alistair Francis |
| 2020-02-27 | target/riscv: Respect MPRV and SPRV for floating point ops | Alistair Francis |
| 2020-02-27 | target/riscv: Mark both sstatus and msstatus_hs as dirty | Alistair Francis |
| 2020-02-27 | target/riscv: Disable guest FP support based on virtual status | Alistair Francis |
| 2020-02-27 | target/riscv: Only set TB flags with FP status if enabled | Alistair Francis |
| 2020-02-27 | target/riscv: Remove the hret instruction | Alistair Francis |
| 2020-02-27 | target/riscv: Add hfence instructions | Alistair Francis |
| 2020-02-27 | target/riscv: Add Hypervisor trap return support | Alistair Francis |
| 2020-02-27 | target/riscv: Add hypvervisor trap support | Alistair Francis |
| 2020-02-27 | target/riscv: Generate illegal instruction on WFI when V=1 | Alistair Francis |
| 2020-02-27 | target/ricsv: Flush the TLB on virtulisation mode changes | Alistair Francis |
| 2020-02-27 | target/riscv: Add support for virtual interrupt setting | Alistair Francis |
| 2020-02-27 | target/riscv: Extend the SIP CSR to support virtulisation | Alistair Francis |
| 2020-02-27 | target/riscv: Extend the MIE CSR to support virtulisation | Alistair Francis |
| 2020-02-27 | target/riscv: Set VS bits in mideleg for Hyp extension | Alistair Francis |
| 2020-02-27 | target/riscv: Add virtual register swapping function | Alistair Francis |
| 2020-02-27 | target/riscv: Add Hypervisor machine CSRs accesses | Alistair Francis |
| 2020-02-27 | target/riscv: Add Hypervisor virtual CSRs accesses | Alistair Francis |
| 2020-02-27 | target/riscv: Add Hypervisor CSR access functions | Alistair Francis |
| 2020-02-27 | target/riscv: Dump Hypervisor registers if enabled | Alistair Francis |
| 2020-02-27 | target/riscv: Print priv and virt in disas log | Alistair Francis |
| 2020-02-27 | target/riscv: Fix CSR perm checking for HS mode | Alistair Francis |
| 2020-02-27 | target/riscv: Add the force HS exception mode | Alistair Francis |
| 2020-02-27 | target/riscv: Add the virtulisation mode | Alistair Francis |
| 2020-02-27 | target/riscv: Rename the H irqs to VS irqs | Alistair Francis |
| 2020-02-27 | target/riscv: Add support for the new execption numbers | Alistair Francis |
| 2020-02-27 | target/riscv: Add the Hypervisor CSRs to CPUState | Alistair Francis |
| 2020-02-27 | target/riscv: Add the Hypervisor extension | Alistair Francis |
| 2020-02-27 | target/riscv: Convert MIP CSR to target_ulong | Alistair Francis |
| 2020-02-25 | target/riscv: progressively load the instruction during decode | Alex Bennée |
| 2020-02-10 | riscv: Separate FPU register size from core register size in gdbstub [v2] | Keith Packard |
| 2020-01-27 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
| 2020-01-24 | qdev: set properties with device_class_set_props() | Marc-André Lureau |
