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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2023-03-01
target/riscv: Coding style fixes in csr.c
Bin Meng
2023-03-01
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
Bin Meng
2023-03-01
target/riscv: gdbstub: Minor change for better readability
Bin Meng
2023-03-01
target/riscv: Use g_assert() for the predicate() NULL check
Bin Meng
2023-03-01
target/riscv: Add some comments to clarify the priority policy of riscv_csrrw...
Bin Meng
2023-03-01
target/riscv: gdbstub: Check priv spec version before reporting CSR
Bin Meng
2023-03-01
Merge patch series "target/riscv: Some updates to float point related extensi...
Palmer Dabbelt
2023-03-01
target/riscv: Expose properties for Zv* extensions
Weiwei Li
2023-03-01
target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc
Weiwei Li
2023-03-01
target/riscv: Fix check for vector load/store instructions when EEW=64
Weiwei Li
2023-03-01
target/riscv: Add support for Zvfh/zvfhmin extensions
Weiwei Li
2023-03-01
target/riscv: Remove redundunt check for zve32f and zve64f
Weiwei Li
2023-03-01
target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc
Weiwei Li
2023-03-01
target/riscv: Simplify check for Zve32f and Zve64f
Weiwei Li
2023-03-01
target/riscv: Indent fixes in cpu.c
Weiwei Li
2023-03-01
target/riscv: Add property check for Zvfh{min} extensions
Weiwei Li
2023-03-01
target/riscv: Fix relationship between V, Zve*, F and D
Weiwei Li
2023-03-01
target/riscv: Add cfg properties for Zv* extensions
Weiwei Li
2023-03-01
target/riscv: Simplify the check for Zfhmin and Zhinxmin
Weiwei Li
2023-03-01
target/riscv: Fix the relationship between Zhinxmin and Zhinx
Weiwei Li
2023-03-01
target/riscv: Fix the relationship between Zfhmin and Zfh
Weiwei Li
2023-03-01
target/riscv/cpu: remove CPUArchState::features and friends
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_MMU
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_PMP
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_EPMP
Daniel Henrique Barboza
2023-03-01
target/riscv/cpu.c: error out if EPMP is enabled without PMP
Daniel Henrique Barboza
2023-03-01
target/riscv: remove RISCV_FEATURE_DEBUG
Daniel Henrique Barboza
2023-03-01
target/riscv: allow MISA writes as experimental
Daniel Henrique Barboza
2023-03-01
target/riscv: do not mask unsupported QEMU extensions in write_misa()
Daniel Henrique Barboza
2023-03-01
target/riscv: introduce riscv_cpu_cfg()
Daniel Henrique Barboza
2023-03-01
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
Richard Henderson
2023-03-01
target/riscv: Replace `tb_pc()` with `tb->pc`
Anton Johansson
2023-02-27
target/riscv/cpu: Move Floating-Point fields closer
Philippe Mathieu-Daudé
2023-02-27
target/cpu: Restrict do_transaction_failed() handlers to sysemu
Philippe Mathieu-Daudé
2023-02-27
target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu
Philippe Mathieu-Daudé
2023-02-23
target/riscv: Fix vslide1up.vf and vslide1down.vf
LIU Zhiwei
2023-02-23
target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
Daniel Henrique Barboza
2023-02-23
target/riscv: Smepmp: Skip applying default rules when address matches
Himanshu Chauhan
2023-02-23
target/riscv: Remove privileged spec version restriction for RVV
Frank Chang
2023-02-08
riscv: Clean up includes
Markus Armbruster
2023-02-07
target/riscv: fix SBI getchar handler for KVM
Vladimir Isaev
2023-02-07
target/riscv: fix ctzw behavior
Vladimir Isaev
2023-02-07
target/riscv: fix for virtual instr exception
Deepak Gupta
2023-02-07
RISC-V: Adding XTheadFmv ISA extension
Christoph Müllner
2023-02-07
RISC-V: Add initial support for T-Head C906
Christoph Müllner
2023-02-07
RISC-V: Set minimum priv version for Zfh to 1.11
Christoph Müllner
2023-02-07
RISC-V: Adding T-Head FMemIdx extension
Christoph Müllner
2023-02-07
RISC-V: Adding T-Head MemIdx extension
Christoph Müllner
2023-02-07
RISC-V: Adding T-Head MemPair extension
Christoph Müllner
2023-02-07
RISC-V: Adding T-Head multiply-accumulate instructions
Christoph Müllner
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