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AgeCommit message (Expand)Author
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-11-14remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata
2019-10-30Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...Peter Maydell
2019-10-28target/riscv: PMP violation due to wrong size parameterDayeol Lee
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt
2019-10-28riscv: Skip checking CSR privilege level in debugger modeBin Meng
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra
2019-09-17riscv: hmp: Add a command to show virtual memory mappingsBin Meng
2019-09-17riscv: rv32: Root page table address can be larger than 32-bitBin Meng
2019-09-17target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis
2019-09-17target/riscv: Create function to test if FP is enabledAlistair Francis
2019-09-17target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace eventsPhilippe Mathieu-Daudé
2019-09-17target/riscv/pmp: Restrict priviledged PMP to system-mode emulationPhilippe Mathieu-Daudé
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen
2019-08-22Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...Peter Maydell
2019-08-21hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster
2019-08-20icount: remove unnecessary gen_io_end callsPavel Dovgalyuk
2019-08-19Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into stagingPeter Maydell
2019-08-19target/riscv: Remove redundant declaration pragmasRichard Henderson
2019-08-19target/riscv: rationalise softfloat includesAlex Bennée
2019-06-25RISC-V: Clear load reservations on context switch and SCJoel Sing
2019-06-25RISC-V: Add support for the Zicsr extensionPalmer Dabbelt
2019-06-25RISC-V: Add support for the Zifencei extensionPalmer Dabbelt
2019-06-25target/riscv: Add support for disabling/enabling CountersAlistair Francis
2019-06-25target/riscv: Remove user version informationAlistair Francis
2019-06-25target/riscv: Require either I or E base extensionAlistair Francis
2019-06-25target/riscv: Set privledge spec 1.11.0 as defaultAlistair Francis
2019-06-25target/riscv: Add the mcountinhibit CSRAlistair Francis
2019-06-24target/riscv: Add the privledge spec version 1.11.0Alistair Francis
2019-06-24target/riscv: Restructure deprecatd CPUsAlistair Francis
2019-06-23RISC-V: Fix a PMP check with the correct access sizeHesham Almatary
2019-06-23RISC-V: Fix a PMP bug where it succeeds even if PMP entry is offHesham Almatary
2019-06-23RISC-V: Check PMP during Page Table WalksHesham Almatary
2019-06-23RISC-V: Check for the effective memory privilege mode during PMP checksHesham Almatary
2019-06-23RISC-V: Raise access fault exceptions on PMP violationsHesham Almatary
2019-06-23RISC-V: Only Check PMP if MMU translation succeedsHesham Almatary
2019-06-23target/riscv: Implement riscv_cpu_unassigned_accessMichael Clark
2019-06-23target/riscv: Fix PMP range boundary address bugDayeol Lee
2019-06-23target/riscv: Allow setting ISA extensions via CPU propsAlistair Francis
2019-06-12Supply missing header guardsMarkus Armbruster
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