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AgeCommit message (Expand)Author
2022-09-13target/riscv: Honour -semihosting-config userspace=on and enable=onPeter Maydell
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra
2022-09-07hw/riscv: virt: Add PMU DT node to the device treeAtish Patra
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra
2022-09-07target/riscv: Add vstimecmp supportAtish Patra
2022-09-07target/riscv: Add stimecmp supportAtish Patra
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li
2022-09-07target/riscv: Add Zihintpause supportDao Lu
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnosti...eopXD
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instruct...Yueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vector load / store instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: rvv: Add mask agnostic for vv instructionsYueh-Ting (eop) Chen
2022-09-07target/riscv: Fix typo and restore Pointer Masking functionality for RISC-VAlexey Baturo
2022-09-07target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_c...Weiwei Li
2022-09-07target/riscv: Fix checks in hmode/hmode32Weiwei Li
2022-09-07target/riscv: Add check for csrs existed with U extensionWeiwei Li
2022-09-07target/riscv: Fix checkpatch warning may triggered in csr_ops tableWeiwei Li
2022-09-07target/riscv: H extension depends on I extensionWeiwei Li
2022-09-07target/riscv: Add check for supported privilege mode combinationsWeiwei Li
2022-09-07target/riscv: move zmmul out of the experimental propertiesWeiwei Li
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot
2022-09-07target/riscv: Force disable extensions if priv spec version does not matchAnup Patel
2022-09-07target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()Anup Patel
2022-09-06target/riscv: Make translator stop before the end of a pageRichard Henderson
2022-09-06target/riscv: Add MAX_INSN_LEN and insn_lenRichard Henderson
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson
2022-09-01meson: remove dead codePaolo Bonzini
2022-07-27RISC-V: Allow both Zmmul and MPalmer Dabbelt
2022-07-03target/riscv: Update default priority table for local interruptsAnup Patel
2022-07-03target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bitsAnup Patel
2022-07-03target/riscv: Set minumum priv spec version for mcountinhibitAnup Patel
2022-07-03target/riscv: Don't force update priv spec version to latestAnup Patel
2022-07-03target/riscv: Ibex: Support priv version 1.11Alistair Francis
2022-07-03target/riscv: Fixup MSECCFG minimum priv checkAlistair Francis
2022-07-03target/riscv: Support mcycle/minstret write operationAtish Patra
2022-07-03target/riscv: Add support for hpmcounters/hpmeventsAtish Patra
2022-07-03target/riscv: Implement mcountinhibit CSRAtish Patra
2022-07-03target/riscv: pmu: Make number of counters configurableAtish Patra
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