| Age | Commit message (Expand) | Author |
|---|
| 2021-10-22 | target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl | Richard Henderson |
| 2021-10-22 | target/riscv: Split misa.mxl and misa.ext | Richard Henderson |
| 2021-10-22 | target/riscv: Create RISCVMXL enumeration | Richard Henderson |
| 2021-10-22 | target/riscv: Move cpu_get_tb_cpu_state out of line | Richard Henderson |
| 2021-10-22 | target/riscv: Organise the CPU properties | Alistair Francis |
| 2021-10-22 | target/riscv: Remove some unused macros | Alistair Francis |
| 2021-10-22 | target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh | Frank Chang |
| 2021-10-22 | target/riscv: Fix orc.b implementation | Philipp Tomsich |
| 2021-10-22 | target/riscv: line up all of the registers in the info register dump | Travis Geiselbrecht |
| 2021-10-22 | target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v | Frank Chang |
| 2021-10-15 | target/riscv: Remove exit_tb and lookup_and_goto_ptr | Richard Henderson |
| 2021-10-15 | target/riscv: Remove dead code after exception | Richard Henderson |
| 2021-10-07 | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty() | Frank Chang |
| 2021-10-07 | target/riscv: Remove RVB (replaced by Zb[abcs]) | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add rev8 instruction, removing grev/grevi | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add a REQUIRE_32BIT macro | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbb-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add instructions of the Zbc-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zbs-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) | Philipp Tomsich |
| 2021-10-07 | target/riscv: Remove the W-form instructions from Zbs | Philipp Tomsich |
| 2021-10-07 | target/riscv: Reassign instructions to the Zba-extension | Philipp Tomsich |
| 2021-10-07 | target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties | Philipp Tomsich |
| 2021-10-07 | target/riscv: clwz must ignore high bits (use shift-left & changed logic) | Philipp Tomsich |
| 2021-10-07 | target/riscv: fix clzw implementation to operate on arg1 | Philipp Tomsich |
| 2021-10-07 | target/riscv: Introduce temporary in gen_add_uw() | Philipp Tomsich |
| 2021-09-21 | hw/core: Make do_unaligned_access noreturn | Richard Henderson |
| 2021-09-21 | include/exec: Move cpu_signal_handler declaration | Richard Henderson |
| 2021-09-21 | target/riscv: csr: Rename HCOUNTEREN_CY and friends | Bin Meng |
| 2021-09-21 | target/riscv: Backup/restore mstatus.SD bit when virtual register swapped | Frank Chang |
| 2021-09-21 | target/riscv: Expose interrupt pending bits as GPIO lines | Alistair Francis |
| 2021-09-21 | target/riscv: Fix satp write | LIU Zhiwei |
| 2021-09-21 | target/riscv: Update the ePMP CSR address | Alistair Francis |
| 2021-09-14 | target/riscv: Restrict cpu_exec_interrupt() handler to sysemu | Philippe Mathieu-Daudé |
| 2021-09-14 | accel/tcg: Add DisasContextBase argument to translator_ld* | Ilya Leoshkevich |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson |
