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AgeCommit message (Expand)Author
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang
2021-12-20target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang
2021-12-20target/riscv: introduce more imm value modes in translator functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update check functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: Use FIELD_EX32() to extract wd fieldFrank Chang
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang
2021-12-20target/riscv: zfh: add Zfhmin cpu propertyFrank Chang
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang
2021-12-20target/riscv: zfh: add Zfh cpu propertyFrank Chang
2021-12-20target/riscv: zfh: half-precision floating-point classifyKito Cheng
2021-12-20target/riscv: zfh: half-precision floating-point compareKito Cheng
2021-12-20target/riscv: zfh: half-precision convert and moveKito Cheng
2021-12-20target/riscv: zfh: half-precision computationalKito Cheng
2021-12-20target/riscv: zfh: half-precision load and storeKito Cheng
2021-11-17target/riscv: machine: Sort the .subsectionsBin Meng
2021-11-02target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson
2021-10-29target/riscv: change the api for RVF/RVD fmin/fmaxChih-Min Chao
2021-10-29target/riscv: remove force HS exceptionJose Martins
2021-10-29target/riscv: fix VS interrupts forwarding to HSJose Martins
2021-10-28target/riscv: Allow experimental J-ext to be turned onAlexey Baturo
2021-10-28target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev
2021-10-28target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo
2021-10-28target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo
2021-10-28target/riscv: Add J extension state descriptionAlexey Baturo
2021-10-28target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo
2021-10-28target/riscv: Add CSR defines for RISC-V PM extensionAlexey Baturo
2021-10-28target/riscv: Add J-extension into RISC-VAlexey Baturo
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson
2021-10-22target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson
2021-10-22target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson
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