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AgeCommit message (Expand)Author
2022-04-22target/riscv: optimize condition assign for scale < 0Weiwei Li
2022-04-22target/riscv: Add initial support for the Sdtrig extensionBin Meng
2022-04-22target/riscv: Allow software access to MIP SEIPAlistair Francis
2022-04-22target/riscv: cpu: Fixup indentationAlistair Francis
2022-04-22target/riscv: Enable privileged spec version 1.12Atish Patra
2022-04-22target/riscv: Add *envcfg* CSRs supportAtish Patra
2022-04-22target/riscv: Add support for mconfigptrAtish Patra
2022-04-22target/riscv: Introduce privilege version field in the CSR ops.Atish Patra
2022-04-22target/riscv: Add the privileged spec version 1.12.0Atish Patra
2022-04-22target/riscv: Define simpler privileged spec version numberingAtish Patra
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau
2022-04-01target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen
2022-04-01target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé
2022-03-06target: Include missing 'cpu.h'Philippe Mathieu-Daudé
2022-03-06misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé
2022-03-03target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li
2022-03-03target/riscv: add support for zhinx/zhinxminWeiwei Li
2022-03-03target/riscv: add support for zdinxWeiwei Li
2022-03-03target/riscv: add support for zfinxWeiwei Li
2022-03-03target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li
2022-03-03target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li
2022-03-03target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich
2022-02-21target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé
2022-02-16target/riscv: add support for svpbmt extensionWeiwei Li
2022-02-16target/riscv: add support for svinval extensionWeiwei Li
2022-02-16target/riscv: add support for svnapot extensionWeiwei Li
2022-02-16target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li
2022-02-16target/riscv: Ignore reserved bits in PTE for RV64Guo Ren
2022-02-16target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel
2022-02-16target/riscv: Implement AIA IMSIC interface CSRsAnup Patel
2022-02-16target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel
2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel
2022-02-16target/riscv: Add AIA cpu featureAnup Patel
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel
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