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AgeCommit message (Expand)Author
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis
2020-02-27target/riscv: Remove the hret instructionAlistair Francis
2020-02-27target/riscv: Add hfence instructionsAlistair Francis
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée
2020-02-10riscv: Separate FPU register size from core register size in gdbstub [v2]Keith Packard
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz
2020-01-24Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf1' i...Peter Maydell
2020-01-16target/riscv: update mstatus.SD when FS is set dirtyShihPo Hung
2020-01-16target/riscv: fsd/fsw doesn't dirty FP stateShihPo Hung
2020-01-16target/riscv: Fix tb->flags FS statusShihPo Hung
2020-01-16riscv: Set xPIE to 1 after xRETYiting Wang
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé
2019-11-14target/riscv: Remove atomic accesses to MIP CSRAlistair Francis
2019-11-14remove unnecessary ifdef TARGET_RISCV64hiroyuki.obinata
2019-10-30Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...Peter Maydell
2019-10-28target/riscv: PMP violation due to wrong size parameterDayeol Lee
2019-10-28target/riscv: fetch code with translator_ldEmilio G. Cota
2019-10-28target/riscv: Make the priv register writable by GDBJonathan Behrens
2019-10-28target/riscv: Expose "priv" register for GDB for readsJonathan Behrens
2019-10-28target/riscv: Tell gdbstub the correct number of CSRsJonathan Behrens
2019-10-28linux-user/riscv: Propagate fault addressGiuseppe Musacchio
2019-10-28RISC-V: Implement cpu_do_transaction_failedPalmer Dabbelt
2019-10-28RISC-V: Handle bus errors in the page table walkerPalmer Dabbelt
2019-10-28riscv: Skip checking CSR privilege level in debugger modeBin Meng
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis
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