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AgeCommit message (Expand)Author
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang
2022-01-21target/riscv: Add host cpu typeYifei Jiang
2022-01-21target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang
2022-01-21target/riscv: Implement kvm_arch_put_registersYifei Jiang
2022-01-21target/riscv: Implement kvm_arch_get_registersYifei Jiang
2022-01-21target/riscv: Implement function kvm_arch_init_vcpuYifei Jiang
2022-01-21target/riscv: Add target/riscv/kvm.c to place the public kvm interfaceYifei Jiang
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis
2022-01-08target/riscv: Fixup setting GVAAlistair Francis
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot
2022-01-08target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot
2022-01-08target/riscv: adding high part of some csrsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit M extensionFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit shift instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot
2022-01-08target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot
2022-01-08target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot
2022-01-08target/riscv: moving some insns close to similar insnsFrédéric Pétrot
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2022-01-08target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot
2022-01-08target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot
2022-01-08target/riscv: additional macros to check instruction supportFrédéric Pétrot
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2022-01-08target/riscv: Fix position of 'experimental' commentPhilipp Tomsich
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang
2022-01-08target/riscv: Enable the Hypervisor extension by defaultAlistair Francis
2022-01-08target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis
2022-01-08target/riscv/pmp: fix no pmp illegal intrsNikita Shubin
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang
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