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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
2022-01-21
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Yifei Jiang
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
2022-01-21
target/riscv: Implement kvm_arch_put_registers
Yifei Jiang
2022-01-21
target/riscv: Implement kvm_arch_get_registers
Yifei Jiang
2022-01-21
target/riscv: Implement function kvm_arch_init_vcpu
Yifei Jiang
2022-01-21
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Yifei Jiang
2022-01-08
target/riscv: Implement the stval/mtval illegal instruction
Alistair Francis
2022-01-08
target/riscv: Fixup setting GVA
Alistair Francis
2022-01-08
target/riscv: Set the opcode in DisasContext
Alistair Francis
2022-01-08
target/riscv: actual functions to realize crs 128-bit insns
Frédéric Pétrot
2022-01-08
target/riscv: modification of the trans_csrxx for 128-bit support
Frédéric Pétrot
2022-01-08
target/riscv: helper functions to wrap calls to 128-bit csr insns
Frédéric Pétrot
2022-01-08
target/riscv: adding high part of some csrs
Frédéric Pétrot
2022-01-08
target/riscv: support for 128-bit M extension
Frédéric Pétrot
2022-01-08
target/riscv: support for 128-bit arithmetic instructions
Frédéric Pétrot
2022-01-08
target/riscv: support for 128-bit shift instructions
Frédéric Pétrot
2022-01-08
target/riscv: support for 128-bit U-type instructions
Frédéric Pétrot
2022-01-08
target/riscv: support for 128-bit bitwise instructions
Frédéric Pétrot
2022-01-08
target/riscv: accessors to registers upper part and 128-bit load/store
Frédéric Pétrot
2022-01-08
target/riscv: moving some insns close to similar insns
Frédéric Pétrot
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
2022-01-08
target/riscv: array for the 64 upper bits of 128-bit registers
Frédéric Pétrot
2022-01-08
target/riscv: separation of bitwise logic and arithmetic helpers
Frédéric Pétrot
2022-01-08
target/riscv: additional macros to check instruction support
Frédéric Pétrot
2022-01-08
exec/memop: Adding signedness to quad definitions
Frédéric Pétrot
2022-01-08
target/riscv: Fix position of 'experimental' comment
Philipp Tomsich
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...
Frank Chang
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...
Frank Chang
2022-01-08
target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...
Frank Chang
2022-01-08
target/riscv: Enable the Hypervisor extension by default
Alistair Francis
2022-01-08
target/riscv: Mark the Hypervisor extension as non experimental
Alistair Francis
2022-01-08
target/riscv/pmp: fix no pmp illegal intrs
Nikita Shubin
2021-12-20
target/riscv: Enable bitmanip Zb[abcs] instructions
Vineet Gupta
2021-12-20
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
Frank Chang
2021-12-20
target/riscv: rvv-1.0: update opivv_vadc_check() comment
Frank Chang
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Frank Chang
2021-12-20
target/riscv: rvv-1.0: add vsetivli instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
2021-12-20
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
Frank Chang
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
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