slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-03-13	target/riscv: Rename trans_arith to gen_arith	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding of RV32/64M insn	Bastian Koppelmann
2019-03-13	target/riscv: Remove shift and slt insn manual decoding	Bastian Koppelmann
2019-03-13	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	Bastian Koppelmann
2019-03-13	target/riscv: Move gen_arith_imm() decoding into trans_* functions	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_store()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_load()	Bastian Koppelmann
2019-03-13	target/riscv: Remove manual decoding from gen_branch()	Bastian Koppelmann
2019-03-13	target/riscv: Remove gen_jalr()	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 1 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV priv insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32D insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64F insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32F insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32A insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXM insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI csr insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI fence insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI arithmetic insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV64I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RV32I load/store insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Convert RVXI branch insns to decodetree	Bastian Koppelmann
2019-03-13	target/riscv: Activate decodetree and implemnt LUI & AUIPC	Bastian Koppelmann
2019-02-11	target/riscv: fix counter-enable checks in ctr()	Xi Wang
2019-02-11	RISC-V: Add misa runtime write support	Michael Clark
2019-02-11	RISC-V: Add misa.MAFD checks to translate	Michael Clark
2019-02-11	RISC-V: Add misa to DisasContext	Michael Clark
2019-02-11	RISC-V: Add priv_ver to DisasContext	Alistair Francis
2019-02-11	RISC-V: Use riscv prefix consistently on cpu helpers	Michael Clark
2019-02-11	RISC-V: Implement mstatus.TSR/TW/TVM	Michael Clark
2019-02-11	RISC-V: Mark mstatus.fs dirty	Richard Henderson
2019-02-11	RISC-V: Split out mstatus_fs from tb_flags	Richard Henderson
2019-01-09	RISC-V: Implement existential predicates for CSRs	Michael Clark
2019-01-09	RISC-V: Implement atomic mip/sip CSR updates	Michael Clark
2019-01-08	RISC-V: Implement modular CSR helper interface	Michael Clark
2019-01-03	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...	Peter Maydell
2018-12-20	riscv/cpu: use device_class_set_parent_realize	Mao Zhongyi
2018-12-20	target/riscv/pmp.c: Fix pmp_decode_napot()	Anup Patel
2018-12-20	RISC-V: Add hartid and \n to interrupt logging	Michael Clark
2018-12-20	Clean up includes	Markus Armbruster
2018-11-13	RISC-V: Respect fences for user-only emulators	Palmer Dabbelt
2018-11-13	target/riscv: Fix sfence.vm/a both available in any priv version	Bastian Koppelmann
2018-11-13	target/riscv: Fix FCLASS_D being treated as RV64 only	Bastian Koppelmann
2018-10-30	target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64	Dayeol Lee
2018-10-17	RISC-V: Update CSR and interrupt definitions	Michael Clark
2018-10-17	RISC-V: Move non-ops from op_helper to cpu_helper	Michael Clark