index
:
slackcoder/qemu
master
QEMU is a generic and open source machine & userspace emulator and virtualizer
Mirror
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
Age
Commit message (
Expand
)
Author
2018-12-20
Clean up includes
Markus Armbruster
2018-11-13
RISC-V: Respect fences for user-only emulators
Palmer Dabbelt
2018-11-13
target/riscv: Fix sfence.vm/a both available in any priv version
Bastian Koppelmann
2018-11-13
target/riscv: Fix FCLASS_D being treated as RV64 only
Bastian Koppelmann
2018-10-30
target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
Dayeol Lee
2018-10-17
RISC-V: Update CSR and interrupt definitions
Michael Clark
2018-10-17
RISC-V: Move non-ops from op_helper to cpu_helper
Michael Clark
2018-10-17
RISC-V: Allow setting and clearing multiple irqs
Michael Clark
2018-09-05
riscv: remove define cpu_init()
Igor Mammedov
2018-09-05
target/riscv: call gen_goto_tb on DISAS_TOO_MANY
Emilio G. Cota
2018-09-05
target/riscv: optimize indirect branches
Emilio G. Cota
2018-09-05
target/riscv: optimize cross-page direct jumps in softmmu
Emilio G. Cota
2018-09-04
RISC-V: Simplify riscv_cpu_local_irqs_pending
Michael Clark
2018-09-04
RISC-V: Improve page table walker spec compliance
Michael Clark
2018-09-04
RISC-V: Update address bits to support sv39 and sv48
Michael Clark
2018-06-08
RISC-V: Add trailing '\n' to qemu_log() calls
Philippe Mathieu-Daudé
2018-06-01
tcg: Pass tb and index to tcg_gen_exit_tb separately
Richard Henderson
2018-05-31
Make address_space_translate{, _cached}() take a MemTxAttrs argument
Peter Maydell
2018-05-18
target/riscv: Honor CPU_DUMP_FPU
Richard Henderson
2018-05-17
target/riscv: Remove floatX_maybe_silence_nan from conversions
Richard Henderson
2018-05-11
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...
Peter Maydell
2018-05-10
target/riscv: Use new atomic min/max expanders
Richard Henderson
2018-05-09
target/riscv: convert to TranslatorOps
Emilio G. Cota
2018-05-09
target/riscv: convert to DisasContextBase
Emilio G. Cota
2018-05-09
target/riscv: convert to DisasJumpType
Emilio G. Cota
2018-05-09
target/riscv: avoid integer overflow in next_page PC check
Emilio G. Cota
2018-05-06
RISC-V: No traps on writes to misa,minstret,mcycle
Michael Clark
2018-05-06
RISC-V: Make mtvec/stvec ignore vectored traps
Michael Clark
2018-05-06
RISC-V: Add mcycle/minstret support for -icount auto
Michael Clark
2018-05-06
RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
Michael Clark
2018-05-06
RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
Michael Clark
2018-05-06
RISC-V: Clear mtval/stval on exceptions without info
Michael Clark
2018-05-06
RISC-V: Hardwire satp to 0 for no-mmu case
Michael Clark
2018-05-06
RISC-V: Update E and I extension order
Michael Clark
2018-05-06
RISC-V: Remove erroneous comment from translate.c
Michael Clark
2018-05-06
RISC-V: Remove EM_RISCV ELF_MACHINE indirection
Michael Clark
2018-03-29
RISC-V: Workaround for critical mstatus.FS bug
Michael Clark
2018-03-28
RISC-V: Convert cpu definition to future model
Michael Clark
2018-03-20
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...
Peter Maydell
2018-03-20
RISC-V: Fix riscv_isa_string memory size bug
Michael Clark
2018-03-19
cpu: add CPU_RESOLVING_TYPE macro
Igor Mammedov
2018-03-07
RISC-V Build Infrastructure
Michael Clark
2018-03-07
RISC-V Linux User Emulation
Michael Clark
2018-03-07
RISC-V Physical Memory Protection
Michael Clark
2018-03-07
RISC-V TCG Code Generation
Michael Clark
2018-03-07
RISC-V GDB Stub
Michael Clark
2018-03-07
RISC-V FPU Support
Michael Clark
2018-03-07
RISC-V CPU Helpers
Michael Clark
2018-03-07
RISC-V CPU Core Definition
Michael Clark