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AgeCommit message (Expand)Author
2018-12-20Clean up includesMarkus Armbruster
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt
2018-11-13target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann
2018-11-13target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
2018-09-05riscv: remove define cpu_init()Igor Mammedov
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell
2018-05-18target/riscv: Honor CPU_DUMP_FPURichard Henderson
2018-05-17target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson
2018-05-11Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell
2018-05-10target/riscv: Use new atomic min/max expandersRichard Henderson
2018-05-09target/riscv: convert to TranslatorOpsEmilio G. Cota
2018-05-09target/riscv: convert to DisasContextBaseEmilio G. Cota
2018-05-09target/riscv: convert to DisasJumpTypeEmilio G. Cota
2018-05-09target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark
2018-05-06RISC-V: Clear mtval/stval on exceptions without infoMichael Clark
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark
2018-05-06RISC-V: Update E and I extension orderMichael Clark
2018-05-06RISC-V: Remove erroneous comment from translate.cMichael Clark
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
2018-03-29RISC-V: Workaround for critical mstatus.FS bugMichael Clark
2018-03-28RISC-V: Convert cpu definition to future modelMichael Clark
2018-03-20Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell
2018-03-20RISC-V: Fix riscv_isa_string memory size bugMichael Clark
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov
2018-03-07RISC-V Build InfrastructureMichael Clark
2018-03-07RISC-V Linux User EmulationMichael Clark
2018-03-07RISC-V Physical Memory ProtectionMichael Clark
2018-03-07RISC-V TCG Code GenerationMichael Clark
2018-03-07RISC-V GDB StubMichael Clark
2018-03-07RISC-V FPU SupportMichael Clark
2018-03-07RISC-V CPU HelpersMichael Clark
2018-03-07RISC-V CPU Core DefinitionMichael Clark