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2019-03-19RISC-V: Add debug support for accessing CSRs.Jim Wilson
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Signed-off-by: Jim Wilson <jimw@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190212230903.9215-1-jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-19RISC-V: Fixes to CSR_* register macros.Jim Wilson
This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Signed-off-by: Jim Wilson <jimw@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190212230830.9160-1-jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-17target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann
during the refactor to decodetree we removed the manual decoding that is necessary for c.jal/c.addiw and removed the translation of c.flw/c.ld and c.fsw/c.sd. This reintroduces the manual parsing and the omited implementation. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Tested-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-13target/riscv: Remove decode_RV32_64G()Bastian Koppelmann
decodetree handles all instructions now so the fallback is not necessary anymore. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove gen_system()Bastian Koppelmann
with all 16 bit insns moved to decodetree no path is falling back to gen_system(), so we can remove it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Rename trans_arith to gen_arithBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann
manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann
gen_arith_imm() does a lot of decoding manually, which was hard to read in case of the shift instructions and is not necessary anymore with decodetree. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_store() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann
We now utilizes argument-sets of decodetree such that no manual decoding is necessary. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Remove gen_jalr()Bastian Koppelmann
trans_jalr() is the only caller, so move the code into trans_jalr(). Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
we cannot remove the call to gen_arith() in decode_RV32_64G() since it is used to translate multiply instructions. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
this splits the 64-bit only instructions into its own decode file such that we generate the decoder for these instructions only for the RISC-V 64 bit target. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
for now only LUI & AUIPC are decoded and translated. If decodetree fails, we fall back to the old decoder. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang
Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang <xi.wang@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa runtime write supportMichael Clark
This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark
Add misa checks for M, A, F and D extensions and if they are not present generate illegal instructions. This improves emulation accurary for harts with a limited set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa to DisasContextMichael Clark
gen methods should access state from DisasContext. Add misa field to the DisasContext struct and remove CPURISCVState argument from all gen methods. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis
The gen methods should access state from DisasContext. Add priv_ver field to the DisasContext struct. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
* Add riscv prefix to raise_exception function * Add riscv prefix to CSR read/write functions * Add riscv prefix to signal handler function * Add riscv prefix to get fflags function * Remove redundant declaration of riscv_cpu_init and rename cpu_riscv_init to riscv_cpu_init * rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Matthew Suozzo <msuozzo@google.com> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson
Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson
Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark
CSR predicate functions are added to the CSR table. mstatus.FS and counter enable checks are moved to predicate functions and two new predicates are added to check misa.S for s* CSRs and a new PMP CPU feature for pmp* CSRs. Processors that don't implement S-mode will trap on access to s* CSRs and processors that don't implement PMP will trap on accesses to pmp* CSRs. PMP checks are disabled in riscv_cpu_handle_mmu_fault when the PMP CPU feature is not present. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark
Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-03Merge remote-tracking branch ↵Peter Maydell
'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging RISC-V Changes for 3.2, Part 1 This pull request contains the first set of RISC-V patches I'd like to target for the 3.2 development cycle. It's really just a collection of bug fixes with one major new feature: PCIe can now be attached to RISC-V guests. This has passed my usual test of booting the latest Linux RC into a Fedora disk image on the virt machine. # gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-3.2-part1: MAINTAINERS: Mark RISC-V as Supported riscv/cpu: use device_class_set_parent_realize target/riscv/pmp.c: Fix pmp_decode_napot() sifive_uart: Implement interrupt pending register RISC-V: Enable second UART on sifive_e and sifive_u RISC-V: Fix PLIC pending bitfield reads RISC-V: Fix CLINT timecmp low 32-bit writes RISC-V: Add hartid and \n to interrupt logging sifive_u: Set 'clock-frequency' DT property for SiFive UART sifive_u: Add clock DT node for GEM ethernet riscv: Enable VGA and PCIE_VGA hw/riscv/virt: Connect the gpex PCIe hw/riscv/virt: Adjust memory layout spacing hw/riscv/virt: Increase the number of interrupts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-20riscv/cpu: use device_class_set_parent_realizeMao Zhongyi
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel
Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark
Add carriage return that was erroneously removed when converting to qemu_log. Change hard coded core number to the actual hartid. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20Clean up includesMarkus Armbruster
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes, with the changes to the following files manually reverted: contrib/libvhost-user/libvhost-user-glib.h contrib/libvhost-user/libvhost-user.c contrib/libvhost-user/libvhost-user.h linux-user/mips64/cpu_loop.c linux-user/mips64/signal.c linux-user/sparc64/cpu_loop.c linux-user/sparc64/signal.c linux-user/x86_64/cpu_loop.c linux-user/x86_64/signal.c target/s390x/gen-features.c tests/migration/s390x/a-b-bios.c tests/test-rcu-simpleq.c tests/test-rcu-tailq.c Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20181204172535.2799-1-armbru@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Acked-by: Yuval Shaia <yuval.shaia@oracle.com> Acked-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt
Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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