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QEMU is a generic and open source machine & userspace emulator and virtualizer
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riscv
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Author
2022-02-21
target: Add missing "qemu/timer.h" include
Philippe Mathieu-Daudé
2022-02-16
target/riscv: add support for svpbmt extension
Weiwei Li
2022-02-16
target/riscv: add support for svinval extension
Weiwei Li
2022-02-16
target/riscv: add support for svnapot extension
Weiwei Li
2022-02-16
target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
Weiwei Li
2022-02-16
target/riscv: Ignore reserved bits in PTE for RV64
Guo Ren
2022-02-16
target/riscv: Allow users to force enable AIA CSRs in HART
Anup Patel
2022-02-16
target/riscv: Implement AIA IMSIC interface CSRs
Anup Patel
2022-02-16
target/riscv: Implement AIA xiselect and xireg CSRs
Anup Patel
2022-02-16
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
Anup Patel
2022-02-16
target/riscv: Implement AIA interrupt filtering CSRs
Anup Patel
2022-02-16
target/riscv: Implement AIA hvictl and hviprioX CSRs
Anup Patel
2022-02-16
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
Anup Patel
2022-02-16
target/riscv: Implement AIA local interrupt priorities
Anup Patel
2022-02-16
target/riscv: Allow AIA device emulation to set ireg rmw callback
Anup Patel
2022-02-16
target/riscv: Add defines for AIA CSRs
Anup Patel
2022-02-16
target/riscv: Add AIA cpu feature
Anup Patel
2022-02-16
target/riscv: Allow setting CPU feature from machine/device emulation
Anup Patel
2022-02-16
target/riscv: Improve delivery of guest external interrupts
Anup Patel
2022-02-16
target/riscv: Implement hgeie and hgeip CSRs
Anup Patel
2022-02-16
target/riscv: Implement SGEIP bit in hip and hie CSRs
Anup Patel
2022-02-16
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
Anup Patel
2022-02-16
target/riscv: Fix vill field write in vtype
LIU Zhiwei
2022-02-16
target/riscv: Add XVentanaCondOps custom extension
Philipp Tomsich
2022-02-16
target/riscv: iterate over a table of decoders
Philipp Tomsich
2022-02-16
target/riscv: access cfg structure through DisasContext
Philipp Tomsich
2022-02-16
target/riscv: access configuration through cfg_ptr in DisasContext
Philipp Tomsich
2022-02-16
target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr
Philipp Tomsich
2022-02-16
target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...
Philipp Tomsich
2022-02-16
target/riscv: correct "code should not be reached" for x-rv128
Frédéric Pétrot
2022-01-21
target/riscv: Relax UXL field for debugging
LIU Zhiwei
2022-01-21
target/riscv: Enable uxl field write
LIU Zhiwei
2022-01-21
target/riscv: Set default XLEN for hypervisor
LIU Zhiwei
2022-01-21
target/riscv: Adjust scalar reg in vector with XLEN
LIU Zhiwei
2022-01-21
target/riscv: Adjust vector address with mask
LIU Zhiwei
2022-01-21
target/riscv: Fix check range for first fault only
LIU Zhiwei
2022-01-21
target/riscv: Remove VILL field in VTYPE
LIU Zhiwei
2022-01-21
target/riscv: Adjust vsetvl according to XLEN
LIU Zhiwei
2022-01-21
target/riscv: Split out the vill from vtype
LIU Zhiwei
2022-01-21
target/riscv: Split pm_enabled into mask and base
LIU Zhiwei
2022-01-21
target/riscv: Calculate address according to XLEN
LIU Zhiwei
2022-01-21
target/riscv: Alloc tcg global for cur_pm[mask|base]
LIU Zhiwei
2022-01-21
target/riscv: Create current pm fields in env
LIU Zhiwei
2022-01-21
target/riscv: Adjust csr write mask with XLEN
LIU Zhiwei
2022-01-21
target/riscv: Relax debug check for pm write
LIU Zhiwei
2022-01-21
target/riscv: Use gdb xml according to max mxlen
LIU Zhiwei
2022-01-21
target/riscv: Extend pc for runtime pc write
LIU Zhiwei
2022-01-21
target/riscv: Ignore the pc bits above XLEN
LIU Zhiwei
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
2022-01-21
target/riscv: Sign extend pc for different XLEN
LIU Zhiwei
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