| Age | Commit message (Expand) | Author |
|---|
| 2024-02-03 | target/riscv: Populate CPUClass.mmu_index | Richard Henderson |
| 2024-02-03 | target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index | Richard Henderson |
| 2024-02-03 | target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index | Richard Henderson |
| 2024-01-31 | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging | Peter Maydell |
| 2024-01-30 | riscv: Clean up includes | Peter Maydell |
| 2024-01-29 | include/qemu: Add TCGCPUOps typedef to typedefs.h | Richard Henderson |
| 2024-01-29 | target: Use vaddr in gen_intermediate_code | Anton Johansson |
| 2024-01-19 | target/riscv: Rename tcg_cpu_FOO() to include 'riscv' | Philippe Mathieu-Daudé |
| 2024-01-10 | target/riscv: Ensure mideleg is set correctly on reset | Alistair Francis |
| 2024-01-10 | target/riscv: Don't adjust vscause for exceptions | Alistair Francis |
| 2024-01-10 | target/riscv: Assert that the CSR numbers will be correct | Alistair Francis |
| 2024-01-10 | target/riscv: pmp: Ignore writes when RW=01 and MML=0 | Ivan Klokov |
| 2024-01-10 | target/riscv/kvm: add RVV and Vector CSR regs | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1... | Yong-Xuan Wang |
| 2024-01-10 | target/riscv: add rva22s64 cpu | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add RVA22S64 profile | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add 'parent' in profile description | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add satp_mode profile support | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/cpu.c: add riscv_cpu_is_32bit() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/cpu.c: finalize satp_mode earlier | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add priv ver restriction to profiles | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: implement svade | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add 'rva22u64' CPU | Daniel Henrique Barboza |
| 2024-01-10 | riscv-qmp-cmds.c: add profile flags in cpu-model-expansion | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: validate profiles during finalize | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: honor user choice for G MISA bits | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: add hash table insert helpers | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: handle profile MISA bits | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: add riscv_cpu_write_misa_bit() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: add MISA user options hash | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: add user flag for profile support | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: add 'rva22u64' flag as unavailable | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add rva22u64 profile definition | Daniel Henrique Barboza |
| 2024-01-10 | riscv-qmp-cmds.c: expose named features in cpu_model_expansion | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: add 'zic64b' support | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add zicbop extension flag | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: add rv64i CPU | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: update priv_ver on user_set extensions | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/tcg: do not use "!generic" CPU checks | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: create TYPE_RISCV_VENDOR_CPU | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv: Add support for Zacas extension | Weiwei Li |
| 2024-01-10 | target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: add RISCV_CONFIG_REG() | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change timer regs size to u64 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/cpu.c: fix machine IDs getters | Daniel Henrique Barboza |
| 2024-01-10 | target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 | Ivan Klokov |
| 2024-01-10 | target/riscv: Not allow write mstatus_vs without RVV | LIU Zhiwei |
