slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-09-17	gdbstub: riscv: fix the fflags registers	KONRAD Frederic
2019-09-17	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point	Alistair Francis
2019-09-17	target/riscv: Fix mstatus dirty mask	Alistair Francis
2019-09-17	target/riscv: Use both register name and ABI name	Atish Patra
2019-09-17	riscv: hmp: Add a command to show virtual memory mappings	Bin Meng
2019-09-17	riscv: rv32: Root page table address can be larger than 32-bit	Bin Meng
2019-09-17	target/riscv: Update the Hypervisor CSRs to v0.4	Alistair Francis
2019-09-17	target/riscv: Create function to test if FP is enabled	Alistair Francis
2019-09-17	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	Philippe Mathieu-Daudé
2019-09-17	target/riscv/pmp: Restrict priviledged PMP to system-mode emulation	Philippe Mathieu-Daudé
2019-09-03	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen
2019-08-22	Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...	Peter Maydell
2019-08-21	hw/core: Move cpu.c, cpu.h from qom/ to hw/core/	Markus Armbruster
2019-08-20	icount: remove unnecessary gen_io_end calls	Pavel Dovgalyuk
2019-08-19	Merge remote-tracking branch 'remotes/rth/tags/pull-dt-20190819' into staging	Peter Maydell
2019-08-19	target/riscv: Remove redundant declaration pragmas	Richard Henderson
2019-08-19	target/riscv: rationalise softfloat includes	Alex Bennée
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis
2019-06-25	target/riscv: Remove user version information	Alistair Francis
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis
2019-06-25	target/riscv: Add the mcountinhibit CSR	Alistair Francis
2019-06-24	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis
2019-06-23	RISC-V: Fix a PMP check with the correct access size	Hesham Almatary
2019-06-23	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	Hesham Almatary
2019-06-23	RISC-V: Check PMP during Page Table Walks	Hesham Almatary
2019-06-23	RISC-V: Check for the effective memory privilege mode during PMP checks	Hesham Almatary
2019-06-23	RISC-V: Raise access fault exceptions on PMP violations	Hesham Almatary
2019-06-23	RISC-V: Only Check PMP if MMU translation succeeds	Hesham Almatary
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark
2019-06-23	target/riscv: Fix PMP range boundary address bug	Dayeol Lee
2019-06-23	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis
2019-06-12	Supply missing header guards	Markus Armbruster
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster
2019-06-11	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson
2019-06-10	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson
2019-06-10	target/riscv: Use env_cpu, env_archcpu	Richard Henderson
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson
2019-06-10	cpu: Define ArchCPU	Richard Henderson
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens