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2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang
Access to a counter in U-mode is permitted only if the corresponding bit is set in both mcounteren and scounteren. The current code ignores mcounteren and checks scounteren only for U-mode access. Signed-off-by: Xi Wang <xi.wang@gmail.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa runtime write supportMichael Clark
This patch adds support for writing misa. misa is validated based on rules in the ISA specification. 'E' is mutually exclusive with all other extensions. 'D' depends on 'F' so 'D' bit is dropped if 'F' is not present. A conservative approach to consistency is taken by flushing the translation cache on misa writes. misa_mask is added to the CPU struct to store the original set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark
Add misa checks for M, A, F and D extensions and if they are not present generate illegal instructions. This improves emulation accurary for harts with a limited set of extensions. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add misa to DisasContextMichael Clark
gen methods should access state from DisasContext. Add misa field to the DisasContext struct and remove CPURISCVState argument from all gen methods. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis
The gen methods should access state from DisasContext. Add priv_ver field to the DisasContext struct. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
* Add riscv prefix to raise_exception function * Add riscv prefix to CSR read/write functions * Add riscv prefix to signal handler function * Add riscv prefix to get fflags function * Remove redundant declaration of riscv_cpu_init and rename cpu_riscv_init to riscv_cpu_init * rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Matthew Suozzo <msuozzo@google.com> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson
Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson
Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark
CSR predicate functions are added to the CSR table. mstatus.FS and counter enable checks are moved to predicate functions and two new predicates are added to check misa.S for s* CSRs and a new PMP CPU feature for pmp* CSRs. Processors that don't implement S-mode will trap on access to s* CSRs and processors that don't implement PMP will trap on accesses to pmp* CSRs. PMP checks are disabled in riscv_cpu_handle_mmu_fault when the PMP CPU feature is not present. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark
Use the new CSR read/modify/write interface to implement atomic updates to mip/sip. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-03Merge remote-tracking branch ↵Peter Maydell
'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging RISC-V Changes for 3.2, Part 1 This pull request contains the first set of RISC-V patches I'd like to target for the 3.2 development cycle. It's really just a collection of bug fixes with one major new feature: PCIe can now be attached to RISC-V guests. This has passed my usual test of booting the latest Linux RC into a Fedora disk image on the virt machine. # gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT # gpg: using RSA key EF4CA1502CCBAB41 # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-3.2-part1: MAINTAINERS: Mark RISC-V as Supported riscv/cpu: use device_class_set_parent_realize target/riscv/pmp.c: Fix pmp_decode_napot() sifive_uart: Implement interrupt pending register RISC-V: Enable second UART on sifive_e and sifive_u RISC-V: Fix PLIC pending bitfield reads RISC-V: Fix CLINT timecmp low 32-bit writes RISC-V: Add hartid and \n to interrupt logging sifive_u: Set 'clock-frequency' DT property for SiFive UART sifive_u: Add clock DT node for GEM ethernet riscv: Enable VGA and PCIE_VGA hw/riscv/virt: Connect the gpex PCIe hw/riscv/virt: Adjust memory layout spacing hw/riscv/virt: Increase the number of interrupts Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-20riscv/cpu: use device_class_set_parent_realizeMao Zhongyi
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel
Currently, start and end address of a PMP region are not decoded correctly by pmp_decode_napot(). Let's say we have a 128KB PMP region with base address as 0x80000000. Now, the PMPADDRx CSR value for this region will be 0x20003fff. The current pmp_decode_napot() implementation will decode PMPADDRx CSR as t1=14, base=0x100000000, and range=0x1ffff whereas it should have decoded PMPADDRx CSR as t1=14, base=0x80000000, and range=0x1fff. This patch fixes the base value decoding in pmp_decode_napot() when PMPADDRx CSR is not -1 (i.e. 0xffffffffffffffff). Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark
Add carriage return that was erroneously removed when converting to qemu_log. Change hard coded core number to the actual hartid. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-20Clean up includesMarkus Armbruster
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes, with the changes to the following files manually reverted: contrib/libvhost-user/libvhost-user-glib.h contrib/libvhost-user/libvhost-user.c contrib/libvhost-user/libvhost-user.h linux-user/mips64/cpu_loop.c linux-user/mips64/signal.c linux-user/sparc64/cpu_loop.c linux-user/sparc64/signal.c linux-user/x86_64/cpu_loop.c linux-user/x86_64/signal.c target/s390x/gen-features.c tests/migration/s390x/a-b-bios.c tests/test-rcu-simpleq.c tests/test-rcu-tailq.c Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20181204172535.2799-1-armbru@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Acked-by: Yuval Shaia <yuval.shaia@oracle.com> Acked-by: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt
Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-11-13target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann
sfence.vm has been replaced in priv v1.10 spec by sfence.vma. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-11-13target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee
pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR. The default promotion rules will result in an integer here ("i*8" is integer, which flows through) resulting in a 32-bit signed value on most hosts. That's bogus on RV64I, with the high bits of the CSR being wrong. Signed-off-by: Dayeol Lee <dayeol@berkeley.edu> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-09-05riscv: remove define cpu_init()Igor Mammedov
cpu_init() was removed since 2.12, so drop the define that is now unused. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota
Performance impact of this and the previous commits, measured with the very-easy-to-cross-compile rv8-bench: https://github.com/rv8-io/rv8-bench Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz - Key: before: master after1,2,3: the 3 commits in this series (i.e. 3 is this commit) - User-mode: bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 1.12s 1.12s 1.10s 1.00s 1.12 bigint 0.78s 0.78s 0.78s 0.78s 1 dhrystone 0.96s 0.97s 0.49s 0.49s 1.9591837 miniz 1.94s 1.94s 1.88s 1.86s 1.0430108 norx 0.51s 0.51s 0.49s 0.48s 1.0625 primes 0.85s 0.85s 0.84s 0.84s 1.0119048 qsort 4.87s 4.88s 1.86s 1.86s 2.6182796 sha512 0.76s 0.77s 0.64s 0.64s 1.1875 (after1 only applies to softmmu, so no surprises here) - Full-system (fedora): bench before after1 after2 after3 final speedup --------------------------------------------------------- aes 2.68s 2.54s 2.60s 2.34s 1.1452991 bigint 1.61s 1.56s 1.55s 1.64s 0.98170732 dhrystone 1.78s 1.67s 1.25s 1.24s 1.4354839 miniz 3.53s 3.35s 3.28s 3.35s 1.0537313 norx 1.13s 1.09s 1.07s 1.06s 1.0660377 primes 15.37s 15.41s 15.20s 15.37s 1 qsort 7.20s 6.71s 3.85s 3.96s 1.8181818 sha512 1.07s 1.04s 0.90s 0.90s 1.1888889 SoftMMU slows things down, so the numbers are less sensitive. Cross-page jumps improve things a little bit, though. Note that I'm not showing here averages, just results from a single run, so with primes there isn't much to worry about. Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota
Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark
This commit is intended to improve readability. There is no change to the logic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
- Inline PTE_TABLE check for better readability - Change access checks from ternary operator to if - Improve readibility of User page U mode and SUM test - Disallow non U mode from fetching from User pages - Add reserved PTE flag check: W or W|X - Add misaligned PPN check - Set READ protection for PTE X flag and mstatus.mxr - Use memory_region_is_ram in pte update Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180606152128.449-11-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate() and address_space_translate_cached(). Callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
2018-05-18target/riscv: Honor CPU_DUMP_FPURichard Henderson
Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson
This is now handled properly by the generic softfloat code. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-11Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180510' into staging target-arm queue: * hw/arm/iotkit.c: fix minor memory leak * softfloat: fix wrong-exception-flags bug for multiply-add corner case * arm: isolate and clean up DTB generation * implement Arm v8.1-Atomics extension * Fix some bugs and missing instructions in the v8.2-FP16 extension # gpg: Signature made Thu 10 May 2018 18:44:34 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180510: (21 commits) target/arm: Clear SVE high bits for FMOV target/arm: Fix float16 to/from int16 target/arm: Implement vector shifted FCVT for fp16 target/arm: Implement vector shifted SCVF/UCVF for fp16 target/arm: Enable ARM_FEATURE_V8_ATOMICS for user-only target/arm: Implement CAS and CASP target/arm: Fill in disas_ldst_atomic target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode target/riscv: Use new atomic min/max expanders tcg: Use GEN_ATOMIC_HELPER_FN for opposite endian atomic add tcg: Introduce atomic helpers for integer min/max target/xtensa: Use new min/max expanders target/arm: Use new min/max expanders tcg: Introduce helpers for integer min/max atomic.h: Work around gcc spurious "unused value" warning make sure that we aren't overwriting mc->get_hotplug_handler by accident arm/boot: split load_dtb() from arm_load_kernel() platform-bus-device: use device plug callback instead of machine_done notifier pc: simplify MachineClass::get_hotplug_handler handling softfloat: Handle default NaN mode after pickNaNMulAdd, not before ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/riscv/translate.c
2018-05-10target/riscv: Use new atomic min/max expandersRichard Henderson
Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180508151437.4232-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-09target/riscv: convert to TranslatorOpsEmilio G. Cota
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Clark <mjc@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-09target/riscv: convert to DisasContextBaseEmilio G. Cota
Notes: - Did not convert {num,max}_insns, since the corresponding code will go away in the next patch. - ctx->pc becomes ctx->base.pc_next, and ctx->next_pc becomes ctx->pc_succ_insn. While at it, convert the remaining tb->cflags readers to tb_cflags(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Michael Clark <mjc@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-09target/riscv: convert to DisasJumpTypeEmilio G. Cota
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Michael Clark <mjc@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-09target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota
If the PC is in the last page of the address space, next_page_start overflows to 0. Fix it. Reported-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Clark <mjc@sifive.com> Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Michael Clark <mjc@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark
Previously the mycycle/minstret CSRs and rdcycle/rdinstret psuedo instructions would return the time as a proxy for an increasing instruction counter in the absence of having a precise instruction count. If QEMU is invoked with -icount, the mcycle/minstret CSRs and rdcycle/rdinstret psuedo instructions will return the instruction count. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark
Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark
The mstatus.MXR alias in sstatus should only be writable by S-mode if the privileged ISA version >= v1.10. Also MXR was masked in sstatus CSR read but not sstatus CSR writes. Now we correctly mask sstatus.mxr in both read and write. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Clear mtval/stval on exceptions without infoMichael Clark
mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark
satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Update E and I extension orderMichael Clark
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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