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AgeCommit message (Expand)Author
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson
2021-09-01target/riscv: Clean up division helpersRichard Henderson
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
2021-07-15target/riscv: hardwire bits in hideleg and hedelegJose Martins
2021-07-15target/riscv: csr: Remove redundant check in fp csr read/write routinesBin Meng
2021-07-15target/riscv: pmp: Fix some typosBin Meng
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell
2021-07-09target/riscv: Use translator_use_goto_tbRichard Henderson
2021-07-09meson: Introduce target-specific KconfigPhilippe Mathieu-Daudé
2021-06-24target/riscv: gdbstub: Fix dynamic CSR XML generationBin Meng
2021-06-24target/riscv: Use target_ulong for the DisasContext misaAlistair Francis
2021-06-08target/riscv: rvb: add b-ext version cpu optionFrank Chang
2021-06-08target/riscv: rvb: support and turn on B-extension from command lineKito Cheng
2021-06-08target/riscv: rvb: add/shift with prefix zero-extendKito Cheng
2021-06-08target/riscv: rvb: address calculationKito Cheng
2021-06-08target/riscv: rvb: generalized or-combineFrank Chang
2021-06-08target/riscv: rvb: generalized reverseFrank Chang
2021-06-08target/riscv: rvb: rotate (left/right)Kito Cheng
2021-06-08target/riscv: rvb: shift onesKito Cheng
2021-06-08target/riscv: rvb: single-bit instructionsFrank Chang
2021-06-08target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang
2021-06-08target/riscv: rvb: sign-extend instructionsKito Cheng
2021-06-08target/riscv: rvb: min/max instructionsKito Cheng
2021-06-08target/riscv: rvb: pack two words into one registerKito Cheng
2021-06-08target/riscv: rvb: logic-with-negateKito Cheng
2021-06-08target/riscv: rvb: count bits setFrank Chang
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