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AgeCommit message (Expand)Author
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson
2022-06-10target/riscv: trans_rvv: Avoid assert for RV32 and e64Alistair Francis
2022-06-10target/riscv: Don't expose the CPU properties on names CPUsAlistair Francis
2022-06-10target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnosti...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector permutation instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector mask instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector reduction instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector floating-point instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instruct...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer merge and move instru...eopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer comparison instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector integer shift instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vector load / store instructionseopXD
2022-06-10target/riscv: rvv: Add tail agnostic for vv instructionseopXD
2022-06-10target/riscv: rvv: Early exit when vstart >= vleopXD
2022-06-10target/riscv: rvv: Rename ambiguous eszeopXD
2022-06-10target/riscv: rvv: Prune redundant access_type parameter passedeopXD
2022-06-10target/riscv: rvv: Prune redundant ESZ, DSZ parameter passedeopXD
2022-06-10target/riscv/debug.c: keep experimental rv128 support workingFrédéric Pétrot
2022-06-10target/riscv: Wake on VS-level external interruptsAndrew Bresticker
2022-06-10target/riscv: add support for zmmul extension v0.1Weiwei Li
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
2022-05-24target/riscv: Change "G" expansionTsukasa OI
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid
2022-05-11Normalize header guard symbol definitionMarkus Armbruster
2022-05-11Clean up ill-advised or unusual header guardsMarkus Armbruster
2022-04-29target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li
2022-04-29target/riscv: Fix incorrect PTE merge in walk_pteRalf Ramsauer
2022-04-29target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li
2022-04-29target/riscv: rvk: add CSR support for ZkrWeiwei Li
2022-04-29target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li
2022-04-29target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li
2022-04-29target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li
2022-04-29target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li
2022-04-29target/riscv: rvk: add support for zbkx extensionWeiwei Li
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