slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2019-06-25	RISC-V: Clear load reservations on context switch and SC	Joel Sing
2019-06-25	RISC-V: Add support for the Zicsr extension	Palmer Dabbelt
2019-06-25	RISC-V: Add support for the Zifencei extension	Palmer Dabbelt
2019-06-25	target/riscv: Add support for disabling/enabling Counters	Alistair Francis
2019-06-25	target/riscv: Remove user version information	Alistair Francis
2019-06-25	target/riscv: Require either I or E base extension	Alistair Francis
2019-06-25	target/riscv: Set privledge spec 1.11.0 as default	Alistair Francis
2019-06-25	target/riscv: Add the mcountinhibit CSR	Alistair Francis
2019-06-24	target/riscv: Add the privledge spec version 1.11.0	Alistair Francis
2019-06-24	target/riscv: Restructure deprecatd CPUs	Alistair Francis
2019-06-23	RISC-V: Fix a PMP check with the correct access size	Hesham Almatary
2019-06-23	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	Hesham Almatary
2019-06-23	RISC-V: Check PMP during Page Table Walks	Hesham Almatary
2019-06-23	RISC-V: Check for the effective memory privilege mode during PMP checks	Hesham Almatary
2019-06-23	RISC-V: Raise access fault exceptions on PMP violations	Hesham Almatary
2019-06-23	RISC-V: Only Check PMP if MMU translation succeeds	Hesham Almatary
2019-06-23	target/riscv: Implement riscv_cpu_unassigned_access	Michael Clark
2019-06-23	target/riscv: Fix PMP range boundary address bug	Dayeol Lee
2019-06-23	target/riscv: Allow setting ISA extensions via CPU props	Alistair Francis
2019-06-12	Supply missing header guards	Markus Armbruster
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster
2019-06-11	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson
2019-06-10	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson
2019-06-10	target/riscv: Use env_cpu, env_archcpu	Richard Henderson
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson
2019-06-10	cpu: Define ArchCPU	Richard Henderson
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson