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AgeCommit message (Expand)Author
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang
2019-02-11RISC-V: Add misa runtime write supportMichael Clark
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark
2019-02-11RISC-V: Add misa to DisasContextMichael Clark
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark
2019-01-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...Peter Maydell
2018-12-20riscv/cpu: use device_class_set_parent_realizeMao Zhongyi
2018-12-20target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark
2018-12-20Clean up includesMarkus Armbruster
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt
2018-11-13target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann
2018-11-13target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark
2018-09-05riscv: remove define cpu_init()Igor Mammedov
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell
2018-05-18target/riscv: Honor CPU_DUMP_FPURichard Henderson
2018-05-17target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson
2018-05-11Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell
2018-05-10target/riscv: Use new atomic min/max expandersRichard Henderson
2018-05-09target/riscv: convert to TranslatorOpsEmilio G. Cota
2018-05-09target/riscv: convert to DisasContextBaseEmilio G. Cota
2018-05-09target/riscv: convert to DisasJumpTypeEmilio G. Cota
2018-05-09target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark